cheeks@UUNET.UU.NET (Mark Costlow) (02/28/90)
[I apologize if you've seen this before. The first time I sent it, it seemed
to go into the bit bucket - I didn't get any bounce messages, but since I
got 0 replies, I'll assume it got lost.]
I'm not sure if this is a bug or a feature. You tell me:
I am trying to use a construct like the one demonstrated in the
following makefile. "all" depends on some program, and that program
depends on the program being built in some other directory ($(BIN)/prog).
Whenever $(BIN)/prog is up-to-date, prog is up-to-date (by my definition).
This all works fine except for one thing: After gnu make has satisfied
itself that all the dependencies for prog have been met, it then tries to
generate a program called "prog", using some default rule from somewhere.
I explicitely do not want make to take any action of this sort, and the
fact that I've put no commands in the "prog:" target should signify that,
shouldn't it? HP make and Sun make both do what I consider to be the right
thing (ie, once the prog1 dependency is satisfied, they exit). (Yes, I
realize that just because HP and Sun do something doesn't make it right ...
and in fact usually indicates otherwise). I suspect the problem is
aggravated by the fact that there is a prog.c in the current directory.
I have a workaround in that putting ANY command in the prog: rule
causes it not to attempt to build a "prog". Even the null command "@" will
prevent it. But, I have a group here with a hierarchy of Makefiles that
use this feature with HP and Sun make, and they don't want to change the
makefiles, so the workaround does me no good. I have another group here
that needs some features that GNU make supplies that HP and Sun make don't,
so I'd rather install GNU make all around.
So, is this a bug in gnu make? Or just a feature?
Mark
Here's the makefile I mentioned above:
------------------------------------------------------------------------------
# Test makefile to demonstate bug in gnu make.
.SUFFIXES:.o .c
DIR = /tmp
BIN = $(DIR)/bin
OBJ = $(DIR)/obj
CC = cc
CFLAGS = -g
.c.o:
$(CC) $(CFLAGS) -c $*.c -o $(OBJ)/$*.o
all: prog
$(BIN)/prog: prog.o
cc -g -o $(BIN)/prog $(OBJ)/prog.o
prog: $(BIN)/prog
------------------------------------------------------------------------------
Here's a sample run with HP make:
<argon> [825] ->make -f makefile.test
cc -g -c prog.c -o /tmp/obj/prog.o
cc -g -o /tmp/bin/prog /tmp/obj/prog.o
-------------------------------------------------------------------------
And here's a sample run with GNU make:
<argon> [827] ->gmake -v -f makefile.test
GNU Make version 3.58, by Richard Stallman and Roland McGrath.
Copyright (C) 1988, 1989, 1990 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.
cc -g -c prog.c -o /tmp/obj/prog.o
cc -g -o /tmp/bin/prog /tmp/obj/prog.o
cc prog.o /tmp/bin/prog -o prog <<<<------- This is the funky line
ld: file prog.o cannot be opened
ld: (Warning) did not generate an output file
gmake: *** [prog] Error 1
-------------------------------------------------------------------------
The line marked funky above is where gnu make decided it wasn't done
and invoked some rule from God-knows-where.
Any input appreciated ...
Mark
cheeks@edsr.eds.com or ...uunet!edsr!cheeks