taylor@THINK.COM (06/10/89)
Here are some changes for GDB's disassembler for the ns32k.
The changes cause GDB
. to print the names of the cpu registers for the lpr and spr
instructions
. to print the names of the mmu registers for the lmr and smr
instructions
. to properly print the 3rd and 4th arguments to the exts and inss
instructions
These changes bring it more in line with what GAS configured for the
ns32k will accept as input, but there are still some discrepancies.
RCS file: RCS/ns32k-opcode.h,v
retrieving revision 1.3
diff -c1 -r1.3 ns32k-opcode.h
*** /tmp/,RCSt1022486 Sat Jun 10 00:34:29 1989
--- ns32k-opcode.h Sat Jun 10 00:33:36 1989
***************
*** 49,51 ****
* p : displacement - pc relative addressing
! */
static struct not
--- 49,60 ----
* p : displacement - pc relative addressing
! * O : setcfg instruction options list
! * C : cinv instruction options list
! * S : string instruction options list
! * U : save/enter register list
! * u : restore/exit register list
! * M : mmu register
! * P : cpu register
! * g : 3rd operand of inss or exts instruction
! * G : 4th operand of inss or exts instruction
! */
static struct not
***************
*** 157,161 ****
{ "extd", 11,24, 0x32e, "2A3D1r4d" },
! { "extsb", 14,24, 0x0cce, "1A2B3i" },
! { "extsw", 14,24, 0x0dce, "1A2W3i" },
! { "extsd", 14,24, 0x0fce, "1A2D3i" },
{ "ffsb", 14,24, 0x046e, "1B2B" },
--- 166,170 ----
{ "extd", 11,24, 0x32e, "2A3D1r4d" },
! { "extsb", 14,24, 0x0cce, "1A2B4G3g" },
! { "extsw", 14,24, 0x0dce, "1A2W4G3g" },
! { "extsd", 14,24, 0x0fce, "1A2D4G3g" },
{ "ffsb", 14,24, 0x046e, "1B2B" },
***************
*** 179,183 ****
{ "insd", 11,24, 0x3ae, "2D3D1r4d" },
! { "inssb", 14,24, 0x08ce, "1B2A3i" },
! { "inssw", 14,24, 0x09ce, "1W2A3i" },
! { "inssd", 14,24, 0x0bce, "1D2A3i" },
{ "jsr", 11,16, 0x67f, "1A" },
--- 188,192 ----
{ "insd", 11,24, 0x3ae, "2D3D1r4d" },
! { "inssb", 14,24, 0x08ce, "1B2A4G3g" },
! { "inssw", 14,24, 0x09ce, "1W2A4G3g" },
! { "inssd", 14,24, 0x0bce, "1D2A4G3g" },
{ "jsr", 11,16, 0x67f, "1A" },
***************
*** 185,190 ****
{ "lfsr", 19,24, 0x00f3e,"1D" },
! { "lmr", 15,24, 0x0b1e, "2D1q" },
! { "lprb", 7,16, 0x6c, "2B1q" },
! { "lprw", 7,16, 0x6d, "2W1q" },
! { "lprd", 7,16, 0x6f, "2D1q" },
{ "lshb", 14,24, 0x144e, "1B2B" },
--- 194,199 ----
{ "lfsr", 19,24, 0x00f3e,"1D" },
! { "lmr", 15,24, 0x0b1e, "2D1M" },
! { "lprb", 7,16, 0x6c, "2B1P" },
! { "lprw", 7,16, 0x6d, "2W1P" },
! { "lprd", 7,16, 0x6f, "2D1P" },
{ "lshb", 14,24, 0x144e, "1B2B" },
***************
*** 332,337 ****
{ "skpst", 16,16, 0x8c0e, "1S" },
! { "smr", 15,24, 0x0f1e, "2D1q" },
! { "sprb", 7,16, 0x2c, "2B1q" },
! { "sprw", 7,16, 0x2d, "2W1q" },
! { "sprd", 7,16, 0x2f, "2D1q" },
{ "subf", 14,24, 0x11be, "1F2F" },
--- 341,346 ----
{ "skpst", 16,16, 0x8c0e, "1S" },
! { "smr", 15,24, 0x0f1e, "2D1M" },
! { "sprb", 7,16, 0x2c, "2B1P" },
! { "sprw", 7,16, 0x2d, "2W1P" },
! { "sprd", 7,16, 0x2f, "2D1P" },
{ "subf", 14,24, 0x11be, "1F2F" },
===================================================================
RCS file: RCS/ns32k-pinsn.c,v
retrieving revision 1.2
diff -c1 -r1.2 ns32k-pinsn.c
*** /tmp/,RCSt1022486 Sat Jun 10 00:34:30 1989
--- ns32k-pinsn.c Fri Jun 9 22:59:20 1989
***************
*** 95,96 ****
--- 95,165 ----
+ #if !defined(NS32032) && !defined(NS32532)
+ #define NS32032
+ #endif
+
+ #if defined(NS32532)
+ struct option cpureg[]= /* lpr spr */
+ {
+ { "us", 0x0, 0xf },
+ { "dcr", 0x1, 0xf },
+ { "bpc", 0x2, 0xf },
+ { "dsr", 0x3, 0xf },
+ { "car", 0x4, 0xf },
+ { "fp", 0x8, 0xf },
+ { "sp", 0x9, 0xf },
+ { "sb", 0xa, 0xf },
+ { "usp", 0xb, 0xf },
+ { "cfg", 0xc, 0xf },
+ { "psr", 0xd, 0xf },
+ { "intbase", 0xe, 0xf },
+ { "mod", 0xf, 0xf },
+ { 0 , 0x00, 0xf }
+ };
+ #endif
+
+ #if defined(NS32532) || defined(NS32382)
+ struct option mmureg[]= /* lmr smr */
+ {
+ { "mcr", 0x9, 0xf },
+ { "msr", 0xa, 0xf },
+ { "tear", 0xb, 0xf },
+ { "ptb0", 0xc, 0xf },
+ { "ptb1", 0xd, 0xf },
+ { "ivar0", 0xe, 0xf },
+ { "ivar1", 0xf, 0xf },
+ { 0 , 0x0, 0xf }
+ };
+ #endif
+
+ #if defined(NS32032)
+ struct option cpureg[]= /* lpr spr */
+ {
+ { "upsr", 0x0, 0xf },
+ { "fp", 0x8, 0xf },
+ { "sp", 0x9, 0xf },
+ { "sb", 0xa, 0xf },
+ { "psr", 0xb, 0xf },
+ { "intbase", 0xe, 0xf },
+ { "mod", 0xf, 0xf },
+ { 0 , 0x0, 0xf }
+ };
+ #endif
+
+ #if !defined(NS32532) && !defined(NS32382)
+ struct option mmureg[]= /* lmr smr */
+ {
+ { "bpr0", 0x0, 0xf },
+ { "bpr1", 0x1, 0xf },
+ { "pf0", 0x4, 0xf },
+ { "pf1", 0x5, 0xf },
+ { "sc", 0x8, 0xf },
+ { "msr", 0xa, 0xf },
+ { "bcnt", 0xb, 0xf },
+ { "ptb0", 0xc, 0xf },
+ { "ptb1", 0xd, 0xf },
+ { "eia", 0xf, 0xf },
+ { 0 , 0x0, 0xf }
+ };
+ #endif
+
/*
***************
*** 125,126 ****
--- 194,208 ----
+ list_search(reg_value, optionP, result)
+ int reg_value;
+ struct option *optionP;
+ char *result;
+ {
+ for (; optionP->pattern; optionP++) {
+ if ((reg_value & optionP->match) == optionP->value) {
+ sprintf(result, "%s", optionP->pattern);
+ return;
+ }
+ }
+ sprintf(result, "undefined");
+ }
***************
*** 482,483 ****
--- 564,585 ----
*aoffsetp += 8;
+ break;
+ case 'M':
+ Ivalue = bit_extract(buffer, ioffset-4, 4);
+ list_search(Ivalue, mmureg, result);
+ ioffset -= 4;
+ break;
+ case 'P':
+ Ivalue = bit_extract(buffer, ioffset-4, 4);
+ list_search(Ivalue, cpureg, result);
+ ioffset -= 4;
+ break;
+ case 'g':
+ Ivalue = bit_extract(buffer, *aoffsetp, 3);
+ sprintf(result, "%d", Ivalue);
+ *aoffsetp += 3;
+ break;
+ case 'G':
+ Ivalue = bit_extract(buffer, *aoffsetp, 5);
+ sprintf(result, "%d", Ivalue + 1);
+ *aoffsetp += 5;
break;taylor@THINK.COM (06/11/89)
[I sent this last night, but it doesn't appear to have been received.]
Here are some changes for GDB's disassembler for the ns32k.
The changes cause GDB
. to print the names of the cpu registers for the lpr and spr
instructions
. to print the names of the mmu registers for the lmr and smr
instructions
. to properly print the 3rd and 4th arguments to the exts and inss
instructions
These changes bring it more in line with what GAS configured for the
ns32k will accept as input, but there are still some discrepancies.
RCS file: RCS/ns32k-opcode.h,v
retrieving revision 1.3
diff -c1 -r1.3 ns32k-opcode.h
*** /tmp/,RCSt1022486 Sat Jun 10 00:34:29 1989
--- ns32k-opcode.h Sat Jun 10 00:33:36 1989
***************
*** 49,51 ****
* p : displacement - pc relative addressing
! */
static struct not
--- 49,60 ----
* p : displacement - pc relative addressing
! * O : setcfg instruction options list
! * C : cinv instruction options list
! * S : string instruction options list
! * U : save/enter register list
! * u : restore/exit register list
! * M : mmu register
! * P : cpu register
! * g : 3rd operand of inss or exts instruction
! * G : 4th operand of inss or exts instruction
! */
static struct not
***************
*** 157,161 ****
{ "extd", 11,24, 0x32e, "2A3D1r4d" },
! { "extsb", 14,24, 0x0cce, "1A2B3i" },
! { "extsw", 14,24, 0x0dce, "1A2W3i" },
! { "extsd", 14,24, 0x0fce, "1A2D3i" },
{ "ffsb", 14,24, 0x046e, "1B2B" },
--- 166,170 ----
{ "extd", 11,24, 0x32e, "2A3D1r4d" },
! { "extsb", 14,24, 0x0cce, "1A2B4G3g" },
! { "extsw", 14,24, 0x0dce, "1A2W4G3g" },
! { "extsd", 14,24, 0x0fce, "1A2D4G3g" },
{ "ffsb", 14,24, 0x046e, "1B2B" },
***************
*** 179,183 ****
{ "insd", 11,24, 0x3ae, "2D3D1r4d" },
! { "inssb", 14,24, 0x08ce, "1B2A3i" },
! { "inssw", 14,24, 0x09ce, "1W2A3i" },
! { "inssd", 14,24, 0x0bce, "1D2A3i" },
{ "jsr", 11,16, 0x67f, "1A" },
--- 188,192 ----
{ "insd", 11,24, 0x3ae, "2D3D1r4d" },
! { "inssb", 14,24, 0x08ce, "1B2A4G3g" },
! { "inssw", 14,24, 0x09ce, "1W2A4G3g" },
! { "inssd", 14,24, 0x0bce, "1D2A4G3g" },
{ "jsr", 11,16, 0x67f, "1A" },
***************
*** 185,190 ****
{ "lfsr", 19,24, 0x00f3e,"1D" },
! { "lmr", 15,24, 0x0b1e, "2D1q" },
! { "lprb", 7,16, 0x6c, "2B1q" },
! { "lprw", 7,16, 0x6d, "2W1q" },
! { "lprd", 7,16, 0x6f, "2D1q" },
{ "lshb", 14,24, 0x144e, "1B2B" },
--- 194,199 ----
{ "lfsr", 19,24, 0x00f3e,"1D" },
! { "lmr", 15,24, 0x0b1e, "2D1M" },
! { "lprb", 7,16, 0x6c, "2B1P" },
! { "lprw", 7,16, 0x6d, "2W1P" },
! { "lprd", 7,16, 0x6f, "2D1P" },
{ "lshb", 14,24, 0x144e, "1B2B" },
***************
*** 332,337 ****
{ "skpst", 16,16, 0x8c0e, "1S" },
! { "smr", 15,24, 0x0f1e, "2D1q" },
! { "sprb", 7,16, 0x2c, "2B1q" },
! { "sprw", 7,16, 0x2d, "2W1q" },
! { "sprd", 7,16, 0x2f, "2D1q" },
{ "subf", 14,24, 0x11be, "1F2F" },
--- 341,346 ----
{ "skpst", 16,16, 0x8c0e, "1S" },
! { "smr", 15,24, 0x0f1e, "2D1M" },
! { "sprb", 7,16, 0x2c, "2B1P" },
! { "sprw", 7,16, 0x2d, "2W1P" },
! { "sprd", 7,16, 0x2f, "2D1P" },
{ "subf", 14,24, 0x11be, "1F2F" },
===================================================================
RCS file: RCS/ns32k-pinsn.c,v
retrieving revision 1.2
diff -c1 -r1.2 ns32k-pinsn.c
*** /tmp/,RCSt1022486 Sat Jun 10 00:34:30 1989
--- ns32k-pinsn.c Fri Jun 9 22:59:20 1989
***************
*** 95,96 ****
--- 95,165 ----
+ #if !defined(NS32032) && !defined(NS32532)
+ #define NS32032
+ #endif
+
+ #if defined(NS32532)
+ struct option cpureg[]= /* lpr spr */
+ {
+ { "us", 0x0, 0xf },
+ { "dcr", 0x1, 0xf },
+ { "bpc", 0x2, 0xf },
+ { "dsr", 0x3, 0xf },
+ { "car", 0x4, 0xf },
+ { "fp", 0x8, 0xf },
+ { "sp", 0x9, 0xf },
+ { "sb", 0xa, 0xf },
+ { "usp", 0xb, 0xf },
+ { "cfg", 0xc, 0xf },
+ { "psr", 0xd, 0xf },
+ { "intbase", 0xe, 0xf },
+ { "mod", 0xf, 0xf },
+ { 0 , 0x00, 0xf }
+ };
+ #endif
+
+ #if defined(NS32532) || defined(NS32382)
+ struct option mmureg[]= /* lmr smr */
+ {
+ { "mcr", 0x9, 0xf },
+ { "msr", 0xa, 0xf },
+ { "tear", 0xb, 0xf },
+ { "ptb0", 0xc, 0xf },
+ { "ptb1", 0xd, 0xf },
+ { "ivar0", 0xe, 0xf },
+ { "ivar1", 0xf, 0xf },
+ { 0 , 0x0, 0xf }
+ };
+ #endif
+
+ #if defined(NS32032)
+ struct option cpureg[]= /* lpr spr */
+ {
+ { "upsr", 0x0, 0xf },
+ { "fp", 0x8, 0xf },
+ { "sp", 0x9, 0xf },
+ { "sb", 0xa, 0xf },
+ { "psr", 0xb, 0xf },
+ { "intbase", 0xe, 0xf },
+ { "mod", 0xf, 0xf },
+ { 0 , 0x0, 0xf }
+ };
+ #endif
+
+ #if !defined(NS32532) && !defined(NS32382)
+ struct option mmureg[]= /* lmr smr */
+ {
+ { "bpr0", 0x0, 0xf },
+ { "bpr1", 0x1, 0xf },
+ { "pf0", 0x4, 0xf },
+ { "pf1", 0x5, 0xf },
+ { "sc", 0x8, 0xf },
+ { "msr", 0xa, 0xf },
+ { "bcnt", 0xb, 0xf },
+ { "ptb0", 0xc, 0xf },
+ { "ptb1", 0xd, 0xf },
+ { "eia", 0xf, 0xf },
+ { 0 , 0x0, 0xf }
+ };
+ #endif
+
/*
***************
*** 125,126 ****
--- 194,208 ----
+ list_search(reg_value, optionP, result)
+ int reg_value;
+ struct option *optionP;
+ char *result;
+ {
+ for (; optionP->pattern; optionP++) {
+ if ((reg_value & optionP->match) == optionP->value) {
+ sprintf(result, "%s", optionP->pattern);
+ return;
+ }
+ }
+ sprintf(result, "undefined");
+ }
***************
*** 482,483 ****
--- 564,585 ----
*aoffsetp += 8;
+ break;
+ case 'M':
+ Ivalue = bit_extract(buffer, ioffset-4, 4);
+ list_search(Ivalue, mmureg, result);
+ ioffset -= 4;
+ break;
+ case 'P':
+ Ivalue = bit_extract(buffer, ioffset-4, 4);
+ list_search(Ivalue, cpureg, result);
+ ioffset -= 4;
+ break;
+ case 'g':
+ Ivalue = bit_extract(buffer, *aoffsetp, 3);
+ sprintf(result, "%d", Ivalue);
+ *aoffsetp += 3;
+ break;
+ case 'G':
+ Ivalue = bit_extract(buffer, *aoffsetp, 5);
+ sprintf(result, "%d", Ivalue + 1);
+ *aoffsetp += 5;
break;ewerlid@mizar.docs.uu.se (Ove Ewerlid) (06/11/89)
I've got the gdb-description of m88k from MCC and they seems to have done quite some work. I can't fully realize what they have done from just the m88k-opcode.h but it looks as if they have included timings of the instructions in the table. I get the impression that they have done a m88k emulator. I will stay low with my dissassembler stuff in GAS until I know what they have done. I have also been forced to make things less reverse enginerable in order to gain speed. I hope to be able to supply you with the new ns32k version of GAS soon. Still one can't tell how long it takes. Ove