ham@polya.Stanford.EDU (Peter R. Ham) (05/31/89)
I'm having some trouble generating assembly code for some rtl for the m68k
backend.
The rtl that I would like to have recognized is:
(insn 3 2 4 (set (reg/i:SI 0)
(mem:SI (plus:SI (symbol_ref:SI ("perprocess_variable"))
(reg:SI 13)))) -1 (nil)
(nil))
I would think that the following pattern in m68k.md would match this instruction:
;; General case of fullword move. The register constraints
;; force integer constants in range for a moveq to be reloaded
;; if they are headed for memory.
(define_insn "movsi"
;; Notes: make sure no alternative allows g vs g.
;; We don't allow f-regs since fixed point cannot go in them.
;; We do allow y and x regs since fixed point is allowed in them.
[(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
(match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
...
...
Does the "g" constraint include data and address registers or not?
I'm assuming that these registers are not considered "general registers",
right? Also, how can it make sense to have the 0 operand, "g" constraint,
be an immediate constant?
What am I missing? I modified the parsing pass of gcc to produce the above
rtl. The vax machine description translations it into valid vax assembly.
On the m68k, the instruction isn't recognized. I would think that the
68020 would be able to handle this, no? I'm thinking that the
PC Indirect With Index (Base displacement) address mode would be used, I don't
need the pc, so the assembler syntax would be:
(bd, ZPC, Xn.SIZE*SCALE)
No?
I would appreciate any help, I'm at a loss.
Peter
--
Peter Ham PO Box 3430 (415) 324-4782
MS Computer Science Student Stanford, CA ham@polya.stanford.edu
Stanford University 94309