ian@sibyl.eleceng.ua.OZ (Ian Dall) (08/27/89)
GCC 1.35 NS32k Systems
-----------------------
I have been porting GCC to an ICM 3216. I have divided the changes I suggest
into two parts. This section has changes which I think should be made to
the generic ns32k.md and tm-ns32k.h files. I believe these changes should
not affect other ns32k (sequent, encore etc) ports but I cannot test those
cases.
The first change is to the "md" file. I have added a JSR_ALWAYS conditional.
I have (NS) assembler which does not convert "bsr"'s to "jsr"'s when it can't
work out the offset (as in the case of branching to an external symbol).
JSR_ALWAYS tells gcc to never generate "bsr" instructions.
Also in the "md" file I have changed some of the match operand
expressions. According to my assembler manual, TBITi instructions
work with a base which can be anything except an immediate operand,
and the offset can be totally general. I think that means the offset
is constraint "g" and the base can be "rm". The 'ns32k.md' file
supplied with gcc 1.27 was definitely wrong in this regard and the
current one seems to have been fixed for some instances and not
others. Am I misunderstanding something here? Anyway I have exercised the
changes below pretty thoroughly by now.
Patches are also included for "tm-ns32k.h". In the supplied tm file
MEM_REG allows SYMBOL_REFs as memory registers and the definition of
INDIRECTABLE_2_ADDRESSES allowed CONSTANT_ADDRESS_P. With those
definitions I had illegal operands like
4(symbol)[r4,d]
It is possible that these fixes interact with the definition of
PRINT_OPERAND and PRINT_OPERAND_ADDRESS. I also have made changes to
those but I am unsure whether my changes are compatible with sequent
addressing bugs and such so I am posting that change in the icm3216
specific posting to follow.
Here are the patches to ns32k.md and tm-ns32k.h
----------------- Cut Here -----------------
*** ../gcc-1.35-dist/config/ns32k.md Thu Aug 17 14:36:06 1989
--- config/ns32k.md Fri Aug 18 00:56:39 1989
***************
*** 1683,1689
[(set (cc0)
(zero_extract (match_operand:SI 0 "general_operand" "rm")
(const_int 1)
! (match_operand:SI 1 "general_operand" "rmn")))]
""
"*
{ cc_status.flags = CC_Z_IN_F;
--- 1683,1689 -----
[(set (cc0)
(zero_extract (match_operand:SI 0 "general_operand" "rm")
(const_int 1)
! (match_operand:SI 1 "general_operand" "g")))]
""
"*
{ cc_status.flags = CC_Z_IN_F;
***************
*** 1694,1700
[(set (cc0)
(compare (zero_extract (match_operand:SI 0 "general_operand" "rm")
(const_int 1)
! (match_operand:SI 1 "general_operand" "rmn"))
(const_int 1)))]
""
"*
--- 1694,1700 -----
[(set (cc0)
(compare (zero_extract (match_operand:SI 0 "general_operand" "rm")
(const_int 1)
! (match_operand:SI 1 "general_operand" "g"))
(const_int 1)))]
""
"*
***************
*** 1704,1710
(define_insn ""
[(set (cc0)
! (zero_extract (match_operand:HI 0 "general_operand" "g")
(const_int 1)
(match_operand:HI 1 "general_operand" "g")))]
""
--- 1704,1710 -----
(define_insn ""
[(set (cc0)
! (zero_extract (match_operand:HI 0 "general_operand" "rm")
(const_int 1)
(match_operand:HI 1 "general_operand" "g")))]
""
***************
*** 1715,1721
(define_insn ""
[(set (cc0)
! (compare (zero_extract (match_operand:HI 0 "general_operand" "g")
(const_int 1)
(match_operand:HI 1 "general_operand" "rmn"))
(const_int 1)))]
--- 1715,1721 -----
(define_insn ""
[(set (cc0)
! (compare (zero_extract (match_operand:HI 0 "general_operand" "rm")
(const_int 1)
(match_operand:HI 1 "general_operand" "g"))
(const_int 1)))]
***************
*** 1717,1723
[(set (cc0)
(compare (zero_extract (match_operand:HI 0 "general_operand" "g")
(const_int 1)
! (match_operand:HI 1 "general_operand" "rmn"))
(const_int 1)))]
""
"*
--- 1717,1723 -----
[(set (cc0)
(compare (zero_extract (match_operand:HI 0 "general_operand" "rm")
(const_int 1)
! (match_operand:HI 1 "general_operand" "g"))
(const_int 1)))]
""
"*
***************
*** 1727,1733
(define_insn ""
[(set (cc0)
! (zero_extract (match_operand:QI 0 "general_operand" "g")
(const_int 1)
(match_operand:QI 1 "general_operand" "g")))]
""
--- 1727,1733 -----
(define_insn ""
[(set (cc0)
! (zero_extract (match_operand:QI 0 "general_operand" "rm")
(const_int 1)
(match_operand:QI 1 "general_operand" "g")))]
""
***************
*** 1738,1744
(define_insn ""
[(set (cc0)
! (compare (zero_extract:SI (match_operand:QI 0 "general_operand" "g")
(const_int 1)
(match_operand:QI 1 "general_operand" "rmn"))
(const_int 1)))]
--- 1738,1744 -----
(define_insn ""
[(set (cc0)
! (compare (zero_extract:SI (match_operand:QI 0 "general_operand" "rm")
(const_int 1)
(match_operand:QI 1 "general_operand" "g"))
(const_int 1)))]
***************
*** 1740,1746
[(set (cc0)
(compare (zero_extract:SI (match_operand:QI 0 "general_operand" "g")
(const_int 1)
! (match_operand:QI 1 "general_operand" "rmn"))
(const_int 1)))]
""
"*
--- 1740,1746 -----
[(set (cc0)
(compare (zero_extract:SI (match_operand:QI 0 "general_operand" "rm")
(const_int 1)
! (match_operand:QI 1 "general_operand" "g"))
(const_int 1)))]
""
"*
***************
*** 2211,2216
""
"*
{
if (GET_CODE (operands[0]) == MEM)
{
if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
--- 2211,2217 -----
""
"*
{
+ #ifndef JSR_ALWAYS
if (GET_CODE (operands[0]) == MEM)
{
if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
***************
*** 2226,2231
return \"jsr %a0\";
#endif
}
return \"jsr %0\";
}")
--- 2227,2233 -----
return \"jsr %a0\";
#endif
}
+ #endif /* ! JSR_ALWAYS */
return \"jsr %0\";
}")
***************
*** 2236,2241
""
"*
{
if (GET_CODE (operands[1]) == MEM)
{
if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
--- 2238,2244 -----
""
"*
{
+ #ifndef JSR_ALWAYS
if (GET_CODE (operands[1]) == MEM)
{
if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
***************
*** 2251,2256
return \"jsr %a1\";
#endif
}
return \"jsr %1\";
}")
--- 2254,2260 -----
return \"jsr %a1\";
#endif
}
+ #endif /* ! JSR_ALWAYS */
return \"jsr %1\";
}")
*** ../gcc-1.35-dist/config/tm-ns32k.h Thu Aug 17 14:35:04 1989
--- config/tm-ns32k.h Thu Aug 17 18:04:01 1989
***************
*** 757,762
&& REG_OK_FOR_BASE_P (XEXP (X, 0)) \
&& CONSTANT_ADDRESS_P (XEXP (X, 1))))
#define MEM_REG(X) \
((GET_CODE (X) == REG && (REGNO (X) ^ 16) < 2) \
|| (GET_CODE (X) == SYMBOL_REF))
--- 757,765 -----
&& REG_OK_FOR_BASE_P (XEXP (X, 0)) \
&& CONSTANT_ADDRESS_P (XEXP (X, 1))))
+ /* Match SP and FP only. This is needed for the 32000
+ "memory relative" addressing mode */
+
#define MEM_REG(X) \
((GET_CODE (X) == REG && (REGNO (X) ^ 16) < 2) \
/*|| (GET_CODE (X) == SYMBOL_REF) -IWD- */)
***************
*** 759,765
#define MEM_REG(X) \
((GET_CODE (X) == REG && (REGNO (X) ^ 16) < 2) \
! || (GET_CODE (X) == SYMBOL_REF))
#define INDIRECTABLE_2_ADDRESS_P(X) \
(GET_CODE (X) == MEM \
--- 762,768 -----
#define MEM_REG(X) \
((GET_CODE (X) == REG && (REGNO (X) ^ 16) < 2) \
! /*|| (GET_CODE (X) == SYMBOL_REF) -IWD- */)
#define INDIRECTABLE_2_ADDRESS_P(X) \
(GET_CODE (X) == MEM \
***************
*** 767,773
|| (GET_CODE (xfoo0) == PLUS \
&& MEM_REG (XEXP (xfoo0, 0)) \
&& CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfoo0, 1)))) \
! || CONSTANT_ADDRESS_P (xfoo0)))
#define INDIRECTABLE_ADDRESS_P(X) \
(INDIRECTABLE_1_ADDRESS_P(X) \
--- 770,776 -----
|| (GET_CODE (xfoo0) == PLUS \
&& MEM_REG (XEXP (xfoo0, 0)) \
&& CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfoo0, 1)))) \
! /*|| CONSTANT_ADDRESS_P (xfoo0) -IWD- */))
#define INDIRECTABLE_ADDRESS_P(X) \
(INDIRECTABLE_1_ADDRESS_P(X) \
--------------- End Of Patch ------------------
--
Ian Dall life (n). A sexually transmitted disease which afflicts
some people more severely than others.