simulation@uflorida.cis.ufl.edu (Moderator: Paul Fishwick) (11/09/89)
Volume: 12, Issue: 5, Thu Nov 9 08:55:00 EST 1989
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| TODAY'S TOPICS |
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(1) Non-Linear Interpolation Software
(2) Rolling Averages/Simulation
(3) Benchmarks for Simulators and HDL Compilers
(4) Model Generation
* Moderator: Paul Fishwick, Univ. of Florida
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Date: Mon, 6 Nov 89 13:44:18 CST
From: honavar@cs.wisc.edu (Vasant Honavar)
To: simulation@bikini.cis.ufl.edu
Subject: Non-linear Interpolation software
Newsgroups: comp.simulation
In-Reply-To:
Organization: U of Wisconsin CS Dept
Cc:
I am looking for non-linear interpolation software tools. If you
know of any (preferably in the public domain), I would appreciate
the information (including pointers to papers/books). Thanks.
______________________________________
Vasant Honavar
Computer Sciences Dept.
University of Wisconsin-Madison
1210 W. Dayton St.
Madison, WI 53706.
honavar@cs.wisc.edu
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Date: Wed, 8 Nov 89 10:53:07 CST
From: wuarchive!wugate!uunet!motcid!marble!reilly@bikini.cis.ufl.edu (Patrick L. Reilly)
To: uflorida!fishwick
Subject: Rolling Averages/Simulation
Consider a buffer of values that are continuously rotating out and periodic sampling of the rolling averages contained in that buffer. Note the difference from the usual moving average concept. I am looking for a good reference point in the literature des
cribing the technique in a simulation environment. Any help?
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Return-Path: news@mipos3.intel.com
Date: 8 Nov 89 18:02:22 GMT
From: sundar@mipos2.intel.com
Subject: Benchmarks for simulators and HDL compilers
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Reply-To: sundar@mipos2.intel.com
Path: mipos3!mipos2.intel.com!sundar
Newsgroups: comp.simulation,comp.arch,comp.lsi
Organization: Hug a Bug Extermination Company, Wilmington, XE.
There are a number of companies that sell simulation systems. Names
such as Gateway (Verilog), Zycad (VHDL, ISP'), Vantage (VHDL) come to
my mind. Are there any standard models to benchmark the various
simulators and languages? I heard that Ron Waxman, who coordinated
much of the VHDL development, had a suite of models, but I don't know
how to reach him.
Thanks.
sundar iyengar
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Sundar Iyengar Microprocessor Design
UUCP: intelca!mipos3!mipos2!sundar Intel, SC4-59
ARPA: sundar@mipos2.intel.com 2625, Walsh Avenue
CSNET: sundar@mipos2.intel.com Santa Clara, CA 95051
AT&T: O: (408) 765-5206
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Return-Path: news@mipos3.intel.com
Date: 9 Nov 89 00:23:38 GMT
From: sundar@mipos2.intel.com
Subject: Model Generation
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To: comp-simulation@uunet.uu.net
Reply-To: sundar@mipos2.intel.com
Path: mipos3!mipos2.intel.com!sundar
Newsgroups: comp.simulation,comp.lsi,comp.arch
Organization: Hug a Bug Extermination Company, Wilmington, XE.
Is any one one familiar with tools to "generate" high level models
for processors and peripherals? Writing a model line at a time is
tedious. Are there tools that given an abstract description,
produces a more detailed model? Something like YACC in Unix would
be along the lines of what I am thinking about. Specify a grammer,
if you will, and have a complete model automatically generated.
I was told of an Israeli company, i-logix, that sells Statemate. In
it, you can graphically describe state machines. A built-in
translator spits out VHDL models for the state machine.
Thanks.
sundar
---------------------------------------------------------
Sundar Iyengar Microprocessor Design
UUCP: intelca!mipos3!mipos2!sundar Intel, SC4-59
ARPA: sundar@mipos2.intel.com 2625, Walsh Avenue
CSNET: sundar@mipos2.intel.com Santa Clara, CA 95051
AT&T: O: (408) 765-5206
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END OF SIMULATION DIGEST
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