simulation@uflorida.cis.ufl.edu (Moderator: Paul Fishwick) (07/16/90)
Volume: 16, Issue: 9, Mon Jul 16 10:49:08 EDT 1990 +----------------+ | TODAY'S TOPICS | +----------------+ (1) International TIMS 1991 (2) RE: Circuit Simulator for MAC II (3) CALL: Object-Oriented Simulation (4) SURVEY: VHDL versus Verilog (LONG MESSAGE) * Moderator: Paul Fishwick, Univ. of Florida * Send topical mail to: simulation@bikini.cis.ufl.edu OR post to comp.simulation via USENET * Archives available via FTP to bikini.cis.ufl.edu (128.227.224.1). Login as 'ftp', use your last name as the password, change directory to pub/simdigest. Do 'type binary' before any file xfers. * Simulation Tools available by doing above and changing the directory to pub/simdigest/tools. ----------------------------------------------------------------------------- To: comp-simulation@cis.ohio-state.edu Path: nisca.ircc.ohio-state.edu!hpuxa.ircc.ohio-state.edu!nelsonb From: nelsonb@hpuxa.ircc.ohio-state.edu (Barry L. Nelson) Newsgroups: comp.simulation Subject: International TIMS 1991 Date: 13 Jul 90 12:47:39 GMT Sender: news@nisca.ircc.ohio-state.edu Organization: The Ohio State University (IRCC) To: Simulation Researchers From: Barry Nelson, VP TIMS College on Simulation Re: International TIMS Meeting in 1991 Date: 7/13/90 The next International TIMS (The Institute of Management Sciences) Meeting is in Rio de Janeiro, Brazil, on July 15-17, 1991. The TIMS College on Simulation has been asked to organize a cluster of sessions for this meeting. I am looking for (informal) proposals from people interested in organizing, chairing or speaking in sessions. A preliminary list of speakers is due August 15, 1990, and the final list is due October 15, 1990. There is no conference proceedings; only a short abstract is required. All attendees, including session chairs and speakers, are required to pay registration fees for the meeting (approximately $250 US). And, of course, it is important that you make every effort to attend the meeting. If you are interested, please contact me as soon as possible (e-mail is best). Barry L. Nelson, Vice President, TIMS College on Simulation Department of Industrial & Systems Engineering The Ohio State University 1971 Neil Avenue Columbus, OH 43210 USA (614) 292-0610 nelson-b@eng.ohio-state.edu ------------------------------ Date: Fri, 13 Jul 90 12:11:18 PDT From: anderson@gloworm.Stanford.EDU To: simulation@bikini.cis.ufl.edu Subject: Re: Circuit Simulator for MAC II Cc: anderson@gloworm.Stanford.EDU This topic recently came up in one of the comp.sys.mac.* newsgroups; three versions of SPICE were mentioned: 1) PSPICE by Microsim. Demo disk available. Supposedly a straight port to the Mac from the PC version. Phone: (800) 826-8603 (714) 770-3022 (714) 770-2415 (customer service) 2) Ispice by Intusoft. Demo disk available for Ispice, prespice, and intuscope programs for the Mac. Phone: (213) 833-9658 3) MacSpice by Deutch Research. Demo disk available. Phone: (415) 327-8677 Fax: (415) 327-0325 It was also mentioned that the BMUG Newsletter of Winter/Spring '90 has a good article from the U. of Hawaii on the subject of circuit analysis. Also, the August '90 issue of MacUser Magazine has a special section concerning CAD tools on the Mac, and a few circuit simulators are mentioned (San Juan Software, Vamp Inc, BV Engineering, Nedrud Data systems etc.) -Greg Anderson Stanford University ------------------------------ To: comp-simulation@bikini.cis.ufl.edu Path: kluge!serss0!ege From: ege@serss0.fiu.edu (Dr. Raimund K. Ege) Newsgroups: comp.simulation,comp.object Subject: Object Oriented Simulation Summary: Call for Papers Date: 15 Jul 90 00:22:44 GMT Sender: news@kluge.fiu.edu Followup-To: comp.simulation Organization: Florida International University, Miami =============================================================== ANNOUNCEMENT AND CALL FOR PAPERS The Society for Computer Simulation Presents ... Object-Oriented Simulation ... part of the 1991 SCS Western Multiconference January 23-25, 1991, Disneyland Hotel, Anaheim, California CALL FOR PAPERS Papers and proposals for panel sessions related to Object-Oriented Simulation are invited. Specific topics include, but are not limited to: - Simulation specification and modeling - Object-oriented architectures - Simulation software, tools and languages - Object-oriented database support - Object-oriented user interfaces - Object distribution and - Visualization networking DEADLINES Papers must contain original contributions. Panel proposal must address topics relevant to object-oriented simulation. All submissions are due August 15, 1990 and will be refereed. Full papers or abstracts may be submitted. Full papers will receive preferential treatment. An abstract must include the title of the proposed paper with a short summary, so that it can be properly positioned in the Conference. Authors must obtain employer, client, or governmental releases prior to submittal of the final manuscript. Authors will be notified of acceptance by September 20, 1990. Camera-ready copy is due October 20, 1990. Authors and other participants are expected to register early, at a reduced rate, and to attend the Conference and participate at their own expense. Submissions with a cover letter stating the name, address, phone number and e-mail address of the authors should be sent to: Dr. Raimund K. Ege Conference Chairman Florida International University School of Computer Science University Park Miami, FL 33199 Tel: (305) 348--3381 FAX: (305) 348--3549 Internet: ege@scs.fiu.edu ------------------------------ Posted-Date: Thu, 12 Jul 90 11:12:02 CDT Date: Thu, 12 Jul 90 11:12:02 CDT From: carpent@src.honeywell.com (Todd Carpenter) To: M.Nigri@uk.ac.ucl.cs, rose@animal.ssec.honeywell.com, hgz@azu.informatik.uni-stuttgart.de, dgg@Solbourne.COM, steven@pacific.csl.uiuc.edu, barton@i2wash.com, cae780!eve!kv@apple.com, turnbull@swindon.nsc.com, clive@uk.ac.man.cs, daniel%cs.man.ac.uk@nfsnet-relay.ac.uk.carson@mcnc.org, dona@bach, simulation@BIKINI.CIS.UFL.EDU, mpulver@adl.austek.oz.au, issi!acosta@cs.utexas.edu, mike.mcmanus@ftcollins, pfy@uk.ac.ed.lfcs, S.LIM@aberdeen.ac.uk, turnbull@swindon.nsc.com, roy@mcnc.org, imken%cadillac.cad.mcc.com@mcc.com, schlesinger@sandiego.ncr.com Subject: VHDL vs Verilof survey I recently posted to UseNet requesting information for an analysis of VHDL versus Verilog. A summary of thought provoking responses follows. I left the message intact for the most part, as I did not feel qualified to extract and enforce any particular interpretation of the many diverse opinions. I leave it to you to read and develop your own opinions. I left the originator's names along with the comments, in case you have specific questions you wish to direct to them. Note that some of the comments will provoke discussion. Remember that all these mailings (including this) carried standard disclaimers about NOT representing the views of any of the associated companies and personnel. This paragraph constitutes a complete discalimer for any liability for any of this stuff. I don't speak legaleze, but I think my intent is clear: This was an *informal* survey, and is thus only a small, non-representative slice of the entire spectrum of people qualified to respond. Furthermore, what is here is *opinion* and not policy. Todd P. Carpenter Honeywell Systems and Research Center voice: (612)782-7229 paper: 3660 Technology Drive, Minneapolis, MN 55418 UUCP: carpent@srcsip.uucp bang-style: {umn-cs,ems,bthpyd}!srcsip!carpent Internet: carpent@src.honeywell.com or Arkon%kryl@src.honeywell.com =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= These are the respondees (In basically random order): Who email Meyer E. Nigri <M.Nigri@uk.ac.ucl.cs> Fred Rose <rose@animal.ssec.honeywell.com> H.-G. Zippererm <hgz@azu.informatik.uni-stuttgart.de> Dan Ganousis <dgg@Solbourne.COM> Steven Parkes <steven@pacific.csl.uiuc.edu> Dave Barton <barton@i2wash.com> Kumar Venkatramani <cae780!eve!kv@apple.com> Keith Turnbull <turnbull@swindon.nsc.com> Clive Holmes <clive@uk.ac.man.cs> Daniel Cock <daniel%cs.man.ac.uk@nfsnet-relay.ac.uk> Carson R. Stuart <carson@mcnc.org> <dona@bach> <simulation@BIKINI.CIS.UFL.EDU> Mark Pulver <mpulver@adl.austek.oz.au> Ramon D. Acosta <issi!acosta@cs.utexas.edu> Mike McManus <mike.mcmanus@ftcollins> Ping Yeung <pfy@uk.ac.ed.lfcs> Steve (Lim?) <S.LIM@aberdeen.ac.uk> <turnbull@swindon.nsc.com> Subhash Chandra Roy <roy@mcnc.org> Gary Imken <imken%cadillac.cad.mcc.com@mcc.com> Steve Schlesinger <schlesinger@sandiego.ncr.com> =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= = Messages follow. Feel free to contact me with questions. All spelling and = = grammar was perfect when I received the messages. Any errors are due to = = noise in the transmission media. = =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: "Meyer E. Nigri" <M.Nigri@uk.ac.ucl.cs> This is a summary of the list of VHDL system suppliers. Of course, it is not complete and subjected to errors. The data in the list were contributed by Fred Rose and mainly by Klaus Ten Hagen. (Suggestions, corrections, critics are welcome) Thanks to those who collaborated. Meyer. ----------------- List of VHDL vendors ------------------------- Company : Intermetrics, Inc. Address : Suite 415 : 4733 Bethesda Ave. : Bethesda, MD 20814 : USA Phone : +1 (617) 661-1840 Fax Phone : +1 (617) 868-2843 Contact : Rachel Rusting Normal Price : $18,000 for 1 year fully-supported licence. University Price: $1,300 limited support per year, per platform : for SUN3 and VAX/VMS. : 2,300 for SUN4 and Apollo. comments : VHDL University Program receives all updates and : releases that are made to the Intermetrics Standard : IEEE 1076 Support Environment during the license : period. This product comprises a VHDL analyzer : and simulator. Company : Mentor Graphics, Inc. Address : 8500 SW Creekside Place : Beaverton, OR 97005 : USA Phone : +1 (503) 526-7000 | (503) 626-1327 Fax Phone : +1 (503) 626 1202 | (503) 626-1268 Contact : ??? | Jon Kregel Normal Price : ??? University Price: see availability Comments : The upcoming VHDL-capable System 1076 seems to be : the best you can get now, System-1076 supports the : whole IEEE-1076 standard, is fully integrated in : the Mentor VLSI design suite, which means you can : get a fast route to silicon, an important issue : nowadays. It has a source level debugger, a fine : waveform display facility and a syntax driven : editor for VHDL. AVAILABILITY : The System-1076 is only available as a beta site : licence for some selected sites. Nevertheless at the : end of this year it will be an integral part of the : release 8. The first release of System 1076 will not : cover the full VHDL language. Release 8 will : not run on Sparcstation, and will run on the SUN : only after mid-1991. The release 8 will run on Apollo, : which is the preferred platform for Mentor yet. : System 1076 will be a free upgrade to existing : Mentor IDEA stations. Company : Synopsis, Inc. Address : First Base | 1098 Alta Ave. : Gilette Way | Mountain View, : Reading, RG2 OBP | CA 94043 : England | USA Phone : ??? | (415) 962-5000 or 962-5050 Fax Phone : ??? | (415) 965-8637 Contact : John Miles | Pierre Wildman Normal Price : ??? University Price: ??? Comments : It seems that Synopsis has no plans to build a : VHDL Simulator. However they do have one of : the best logic synthesis tools available, : which create logic from VHDL and Verilog : descriptions, and also an excellent optimization tool. Company : Zycad Corp. Address : 10 Madison Ave. | 20 Burlington Mall Road, Suite 401 : Morristown, NJ 07960 | Burlington, Massachusetts 01803 : USA | USA Phone : +(201) 538-7833 | +1 (617) 273 2281 Fax Phone : ??? | ??? Contact : ??? | Larry Beecher UK Address : West Lodge, Station Approach : West Byfleet, : Surrey, KT14 6NG UN Phone : 09323 53957 UK Fax Phone : 09323 54378 UK Contact : Anthony Boylan Normal Price : $44,000 (One seat license for a SUN3 and SUN4/1XX : $66,000 (for a SUN4/2XX and SparcStation) University Price: reduction of 20%. Comments : Zycad supports now the full VHDL language. : It has a versatile source-level debugger, a very : fast analyzer, and a syntax-directed editor. : Zycad purchased Endot, which had a : sophisticated simulator and was working on a : VHDL simulator at the time of purchase. Company : Vantage Analysis Systems, Inc. Address : Suite 201 | Westward House : 42840 Christy St. | Montrose Avenue : Fremont, CA 94538 | Slough SL14TN : USA | UK Phone : +1 (415) 659-0901 | 44-0-753-38081 Fax Phone : +1 (415) 659 0129 | 44-0-753-511308 Contact : John Wiley | Richard K. Hall Normal Price : from 30,000 to 60,000 ??? University Price: ??? Machines : Apollo DN3000-4000 and SUN3, and soon on Sun : SparcStations Comments : The Vantage VHDL System is a stand alone : product, but has several options for integrating : it into existing VLSI tool suites. Vantage can : import graphical schematic data from the Mentor : tool suite. EDIF 2 0 0 schematics can be both : imported from and exported to VHDL. A : specialised schematic editor lets the engineer : make on-the-fly changes to the design, since : no compilation is needed (it executes the models : in the data base representing the design). : This avoids the long time required to recompile : it, which makes it very fast. It also includes a : very good symbolic debugger. Company : CADENCE Design Systems, Inc. Address : Two Lowell Research Center Drive : Lowell, MA 01852-4995 : USA Phone : +1 (408) 943 1234 Fax Phone : +1 (408) 943 0513 Contact : ??? Normal Price : ??? University Price: ??? Comments : Cadence has bought Gateway Design Automation : Corp. and thus they have the Verilog HDL with : simulator. For this Verilog HDL they offer a : compiler to VHDL, the so called Vdoc. : : The real VHDL simulation facility is announced : for the end of this year. The product is called : VHDL-XL and it's not a full VHDL simulator, rather : an usual digital logic simulator. VHDL-XL supports : build-in primitives like NAND, NOR and XOR and a : bounded set of logic states with eight levels of : signal strength. Hence it is not the right tool for : system simulation since there are no complex data : types available. : Nevertheless it's an useful tool because it brings : an end to the incompatibility problems you have if : you want to simulate your chip with the standard : cell library of another vendor. Company : Logic Automation Address : Farley Hall : London Road : Bracknell, Berks RG12 5EU : UK Phone : +44 344 863230 Fax Phone : +44 344 863990 Contact : ??? Normal Price : ??? University Price: ??? Comments : Logic Automation has developed a lot of VHDL : libraries for nearly all popular logic families : like AS, HCMOS, ACL 100K ECL ... They have also : models for other more complex standard LSI/VLSI : chips. They have more than 2.500 models of : integrated circuits up to rather complex ones : like Intel 80386 and Motorola 68030. Company : MCC Address : 3500 West Balcones Center Dr. : Austin, Texas 78759 : USA Phone : +1 (512) 338 3794 Fax Phone : ??? Contact : ??? Normal Price : ??? University Price: ??? Comments : They have a VHDL simulator that complies to the : full IEEE 1076 standard. It runs on SUN3, Sun4 : and Apollo 3500 machines. It seems that : their system has an interface to C, which : can be very important for you if you have C : models of your system. : However it seems that they deliver only to the : US and Canada. MCC compiler will be used by Cadence. : Otherwise you have to be a member. MCC has certain : limitation placed on them by the government because : they are a consortium. Company : Viewlogic Systems Inc. Address : 313 Boston Post Road : Marlboro : MA 01752 Phone : (508) 480-0881 Fax Phone : (508) 480-0882 Contact : Oz Levia (e-mail: olevia@viewlogic.com) Normal Price : ??? University Price: ??? Machines : It runs on Sun4 and SparcStation. Comments : Subset now available on IBM PC 386-based that : runs UNIX. They also have VHDL-based logic synthesis. : They are not as well know as some of the other : vendors but have a very good product that is : widely used. - Dazix has added VHDL capability and logic synthesis tools to its EDA product line. - Silvar-Lisco with its Helix language and simulator and Gateway Design Automation with its Verilog simulation system and language - Silc Technologies Inc. of Burlington, Mass. has a logic synthesis from VHDL. Silc was recently purchased by Racel-Redac which is developing a VHDL simulator. - Silicon Compilers: Plans unknown since they were purchased by Mentor. - Gateway Design Automation Corp. (Lowell, Mass.) is now part of Cadence called the Advance CAE Division. - Praxis will support VHDL by offering a translator between ELLA and VHDL this year. - There are others.... ------------------- End of the list of VHDL vendors -------------------- =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: "Fred Rose" <rose@animal.ssec.honeywell.com> To compare the two as objectively as possible, several areas need to be examined: Technical capabilities Performance Integration Price Technical Capabilities Both VHDL and Verilog can be considered "modern" HDLs. They were both designed in the mid-80's after there can been about 10 years of widespread, but still relatively small, usage of HDLs. Verilog was of course written by a small group of people who developed a simulator in conjunction with the language. Therefore the simulator and the language are optimized for each other. VHDL was also developed by a small group of people but had vastly different objectives and was reviewed by many people during its development. There was no simulator designed in conjunction with the language. The language in many ways are quite similar. Both have concurrent and sequential statements. Both have the equivalent of a VHDL process statement, that is a sequential bit of code which executes concurrently as part of a larger simulation. VHDL has much greater modeling capabilities in terms of flexibility and range of design abstraction that can be modeled, mostly at the higher end. This flexibility, however is also a disadvantage in some cases since it presents too many choices to the designer, particularly in the area of synthesis. Registers are a case in point. Verilog has a specific construct for a register; VHDL does not. Each synthesis tool specifies what they expect a register to look like. This is why VHDL is criticized as being not well suited for synthesis. The other main technical difference is in the area of logic states. Verilog has a fixed number of states and the user cannot define his own. VHDL leaves the definition of states completely up to the user. This is an extremely powerful feature that allows the creation of abstract states (PUSH, POP, CLR, etc.) for high level modeling. Again the flexibility can be viewed as a disadvantage at times because it is another degree of freedom to control Beyond those, I think the capabilities are about the same. Verilog is a sparser language in terms of verbiage. To compare the languages on a construct by construct basis strikes me as being too far in the noise level. Integration: Verilog was recently put in the public domain. This is good since some companies that have Verilog toolkits may release them as products and in general makes the language more accessible. However, it is unlikely anyone will build and market a Verilog simulator, besides Cadence. That means a sole source. VHDL is by very definition, simulator/vendor independent. This is a tremendous advantage since it provides data and vendor independence. The problem with that so far is the slowness with which the vendors are coming up to speed on the whole language. Only Zycad and Intermetrics have the full language to date. The subset issue is short term (I guess another 2 years) but still a troublesome issue. VHDL will be integrated nicely into Mentors 8.0 environment. I don't expect great performance with 8.0 and 8.0 will not have the full language either. However, the ability to mix BLMs and VHDL models, along with the whole concurrent engineering concept of 8.0 provides a good path into HDL based design and better integration of design functions. Release 8.0 from Mentor provides a potential for improvements in the design process from box down to IC. Board simulation with Verilog is something I don't know much about. I don't know if Verilog models are available from LAI. I also don't know the ease of which that simulation can be accomplished and whether the other simulation aids Mentor provides (HML, Quickparts, etc.) are available to Verilog. Honeywell has a corporate library of standard parts (BLMs) and is also working on a corporate licensing agreement with LAI for Mentor BLMs. There are internal {Honeywell} VHDL training classes and tools available. SSOC is blazing a trail for VHDL synthesis. There is a lot of knowledge available for sharing and bringing a design group rapidly up the learning curve. There is nothing available for Verilog. What is the long term outlook? VHDL will be around for a long time. Verilog has too big a user base to disappear any time soon. Long term they may both co-exist for some time to come with VHDL being the dominant language. Too many vendors are committing to VHDL for it to disappear. Performance Verilog is widely considered to be the faster simulation available and I have seen no data to dispute that. Verilog is about 5 times faster than Quicksim. Mentor claims Quicksim II beats Verilog but that remains to be seen. The Vantage simulator is faster than Quicksim (benchmarked) but does not approach Verilog (educated guess). HDL simulation consists of two parts - compile and simulate. Verilog compiler is extremely fast. Verilog is compiled into a intermediate form that is executed directly by the Verilog kernel. VHDL tools generally either take that approach or take the approach of compiling VHDL into C and executing the C code as the simulation kernel. Zycad takes a Verilog like approach and has similar compiler performance to Verilog (again educated guess but I saw an 8000 line model compiled by Zycad on a Sun 4 in less than 10 secs. The demo I saw of Verilog was similar in speed). However the simulator performance of Zycad is nowhere near that of Verilog. Zycad always has the accelerated VHDL option for structure. Performance is such a complicated issue. Behavioral models perform much better than structural models and one can simulate a much larger design modeling it behaviorally rather than structurally. Also something to consider besides CPU performance is design process performance. This is related to integration and tool capabilities. Debugging is probably the best example. Verilog provides a symbolic debugger. So do Vantage and Zycad, although Vantage's is probably better. Bottom line on performance: Verilog is faster overall. Unlikely a VHDL simulator will beat it except for Cadence's own VHDL product. Price : Verilog is probably more expensive than the VHDL products but price needs to be worked on an individual basis. Vantage and Zycad are both around $25-$30 K. VHDL Options: Zycad and Vantage obviously. Cadence's VHDL product will be high performing but in the first release will only do the Verilog state system. Still, something to consider. Viewlogic also has a VHDL product, limited now but they are working on a full implementation. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: dgg@Solbourne.COM (Dan Ganousis) I am the ASIC Design manager here at Solbourne Computer - we design Sun-compatible workstations, I don't know if you are familiar with our company as we've only been around 3 years. I am presently trying to make a BIG decision whether to go with Verilog or VHDL - so I was interested in your posting and the responses you get. I'm going to DAC later this month where I hope to get a chance to see all the players and their products up close and personal, so when I get back I'll forward you my impressions. As of now, here's my 2cents worth ... 1. I don't like the VHDL language - it's overly verbose, cumbersome and overkill for behavioral modelling of hardware. I appreciate that they were trying to develop a language "all-encompassing" of the design project - but if I were in the middle of a large dewsign project, the language would be a big nuisance. 2. We have used Synopsys here for 2 years and have developed 7 ASICs to date (real silicon, real hardware) by writing RTL descriptions and synthesizing the gate level designs. It works - it works very well. Our design productivity is 50 per cent greater than our old way of drawing schematics using VTItools. My concern is that Synopsys will lean towards VHDL (because they think WE (the industry) want them to) and move farther apart from Verilog - in fact, I've heard rumors that Synopsys may buy a VHDL simulator company. This scares me if I decide to go Verilog. 3. If VHDL is so great, why are the big boys all buying Verilog?? Recently I know that Compaq went Verilog - and of course Sun, Apple, Amdahl, Cypress/Ross, etc etc are all Verilog users. Is it maybe that VHDL addresses the lower echelon of designers? ie, the same market that Viewlogic and Mentor serve - what I mean is that sophisticated designers will probably be bothered by VHDL - the straightforward style of Verilog probably is preferred in my environment. 4. Wasn't Ada the DoD programming language of the future? Is VHDL going to go the way of Ada??? 5. I haven't seen a good VHDL simulator yet - I'll let you know after DAC. I look forward to hearing what others have to say - thanks for your effort in gathering this information. Dan Ganousis Solbourne Computer 1900 Pike Road Longmont, CO 80501 (303)678-4306 email: dgg@Solbourne.com From: carpent@src.honeywell.com (Todd Carpenter) > 1. I don't like the VHDL language - it's overly verbose, That was my impression at first as well. As was my impression of Ada. But I have written quite a lot in a number of HDLs, C, and Ada. It turns out that Ada *is* appropriate for a goodly number of things! However, I still do my high speed, optimized math in C. Probably a similar correlation can be done with VHDL. Sure, it is verbose. However, I don't see Verilog as any better. ISP' is terrible, Simscript isn't appropriate for this stuff, and Helix is quite outdated. Do you remember what version of vhdl you looked at before? The old 7.2 was significantly more verbose, and was incredibly ugly. The current standard, 1076, is much cleaner. I wouldn't say it is as lean as C is, for instance, but if you replace all your { with BEGIN, and } with END, you'll see that VHDL isn't too far off. What VHDL buys you for behavioral: ( Definition of levels. I am working well above RTL at this point in time.) and down at RTL is extremely tight and strong type consistency. As I write my models, I find the compiler is catching quite a few errors that would have gotten through other compilers. This means that some of that VHDL overhead is being used to constrain me into writing more hardware oriented models. It took me a long time to get used to that (as it did with Ada), but I am seeing the payoff in drastically reduced debug efforts. > 3. If VHDL is so great, why are the big boys all buying Verilog?? My opinion is because the VHDL tools are not sufficiently mature. Perhaps we view VHDL differently. I feel that VHDL makes a lousy low level design language. That is the level where you want tools to do the work for you. I would *never* write a gate or even RTL level description in VHDL. There, your complaints about verbosity are quite valid. However, I would use a tool where I can do schematic capture and let the tool spit out the vhdl for me. And I'll never even see the vhdl, because the synthesis tools take it from there. Vantage has such a schematic capture system. > 4. Wasn't Ada the DoD programming language of the future? Is VHDL > going to go the way of Ada??? Yes, people learn all the time. But Ada does have it's place. And so always will C and LISP. (No, Pascal no longer has a place. Ada does everything Pascal did, and much better/faster). I think VHDL will follow the same track. I am not entirely convinced it is appropriate at extrememly high levels, such as in stochastic system level simulations. But that is an entirely different topic. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: barton@i2wash.com First of all, Honeywell has a well-known VHDL expert in Fred Rose, in your Plymouth, MN plant. As a check on any answers I might give, I suggest that you get in touch with him. In particular, he has looked at a variety of VHDL toolsets, and has opinions about them. As far as learning curve is concerned, you have punched one of my buttons. I believe that learning curve is far more a product of internal procedures than of the language being learned. Frequent, caustic reviews of code written by team members increases the learning curve more than any training technique with which I am familiar. We have not done any surveys of previous course members. In general, their plans concerning future VHDL use are sufficiently vague (and different) that such a survey would not be of much use. If I were to compare it to something, I would compare it to learning to program in a complex language for the first time. This can take a while. Using a subset (particularly a structural subset) of the language is easier, and happens more quickly. I have little long term experience with hardware engineers. I suggest getting in touch with Fred. I don't know Verilog that well. I do know that Cadence is planning a VHDL implementation very soon. You might want toget in touch with them, if they are your major vendor. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: "Fred Rose" <rose@animal.ssec.honeywell.com> How long does it take {To learn the language} ? Depends on the experience level of the designer and how much he knows about software and simulation. The average ASIC designer is typically young (Less that 35, young gets older all the time) and is pretty computer literate so the experience level is high, therfore learning curve is short. You are probably a quicker learner than most because of your experience but probably not by a lot for good designers. I have seen people go through the class and start to work on real projects. After a few weeks they are prodcutive and turing out code. Just like anything you continue to learn, but a "usable subset" can be learned in a few weeks. Your point about higher probability of correct model is valid. However, sometimes the verbosity of VHDL can get in the way. I don't have any stats for you on this. XX referred to learning a structural subset. Sure that is easy but what good does it do you? Structure should be synthesized anyway. By giving a designer a good logic package, some useful functions, and a style to use for RTL, they can comne up to speed pretty fast. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: Ping Yeung <pfy%LFCS.ED.AC.UK@CORNELLC.cit.cornell.edu> > I am currently involved in a tradeoff of VHDL vs. Verilog. I know very little about Verilog(we cannot afford Cadence's Verilog Simulator). However, I do know something about VHDL. We start teaching VHDL in our MSc cources this year and we have the VHDL simulator from Intermetrics. > Language Features I think everyone will tell you VHDL covers description in behavioral, dataflow and structural level. That's true. Actually, it is very flexible. It covers the scope of ADA to gate level description. However, just because of that, it is easy to mix up sometime. Some of our students ask "When we should use.....". There is no definite answer to this queston. I think it is why people are trying to establish simulation subset or synthesis subset of the language. To my experience, the language is quit different to learn. Someone said it just like learning 3 languages and then mix them up. So if you are interested in description in one level, it is easy. And if the vendor can supply a good set of example, it definite will help. > Performance > Ease of use > Compiler Speed > Runtime Speed > Design iteration speed The compiler speed of Intermetrics's simulator is definitely not fast at all on SUN3 machine(compare with cc). Zycad claim they have the fastest compiler but I haven't seen it. Howver, because complex features offered by the language, I think it is acceptable. The debugging support of Intermetrics is not good enough(not interactive). Others like Mentor, Zycad do this much better. Comparing with designs described in C, the bug fixing iteration speed of VHDL is slow. However, when you start to move the design toward structural implementation, VHDL can follow the design process to move downward while others like C can't. This is the major advantage of VHDL. In addition, it is important to notice the difference between simulation description vs synthesis description. Although, Synopsis claim they can take designs in Verilog, they have a input policy which says how the design should be written. One very obvious example is the error report statement(print) or assert in VHDL. Moveover, I seem to remember someone has pointed out that the "always" statement in Verilog could cause problem as well. All in all, I think many people will agree that description written with simulation in mind will be quit different from the synthesis counterpart. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: S.LIM@aberdeen.ac.uk Here are some comments on VHDL vs Verilog. My experience with VHDL is in the development of a behavioural synthesis system while my experience with Verilog is limited to that of a cursory user although I have written translators for it. Comparing VHDL with Verilog is like comparing langauges like Ada and Occam in that one, being a standard, is designed from the outset to provide a general set of constructs to cater for a wide variety of users while the other, being proprietary, is targetted at a more application-specific and thus restricted user domain. The contrast is more so with hardware description languages because applications based on an HDL tend to have very specific selling points so that only certain features of the language concerned are emphasised. I will comment mostly on language features. Data types ---------- VHDL has no built in data types. All types are defined, but a core of key types such as integer, bit, boolean, are provided as part of a 'predefined language environment' as defined by the reference manual. Their definitions are given in a standard package (akin to a C .h file) to be included by an application albeit automatically. Using type definitions, virtually any conceivable type can be created, but an application usually requires some restriction on types to be practical. An example is in the definition of logic-value types. Typically, this is done with an enumeration such as type MVL is ('0', '1', 'X', 'Z'); A data oject declared to be of this type is intuitively to be realised by a single bit (wire or flipflop) instead of two (for four values). But how does an application treat other enumerations such as type Instruction is ( -- 128 enumerated instructions ); which requires 7 bits? VHDL vendors typically support a fixed set of hardware data types. Verilog has a set of built in types and does not support user-defined types. So every type has precise and unambiguous semantics which the application under- stands. Moreover, types pertaining to hardware such as net and gate types have specific hardware characteristics inbuilt e.g. wired-or, wired-and, or a net connecting to supply. For a synthesis application, memory types may be useful. In VHDL amemory is typically described by an array of bit-vectors. The application therefore has to adopt some langauge 'pragma' (not extension) to differentiate memory objects from other arrays (even a bit-vector is an array - of bits). Verilog has no such problem - a specific memory type is provided. Imperative constructs --------------------- Pascal-like statements for algorithmic description are comparable in both languages and the contrast is in the level of syntactic convenience. However, Verilog has certain statements that allow very convenient user control of hardware behaviour, or a simulation run, through event and delay control state- ments. In VHDL, one has to make use of predefined attributes, guards, and time expressions in assignment statements which many users have found unwieldy to use at times. Applications interface ---------------------- VHDL has no defined interface to system tasks and this is vendor-specific. System calls if embedded in the VHDL code makes the VHDL non-portable. Verilog supports system tasks as part of the langauge and the interface to other applica- tions such as simulators ,debuggers, and graphical displays is well defined. Component instantiations ------------------------ Verilog supports specific builtin gate primitives with user-definable drive strengths and delays. Users may define their own primitives although these are restricted to a truth table or a finite state table description. At the highest level of component abstraction is the module. In a module, gates, uer-defined primitives and other modules may be instantiated. VHDL understands no such component hierarchy. Every component is an entity in itself, even primitives. Again, an application has to provide its own set of primitives and the user typically defines drive strength and delay through its 'generics' or 'attributes'. Component hierarchy is derived through the description , i.e. lower level components are instantiated within higher level components. Verilog has a powerful way for connecting nets and ports of instantiated components. In particular the nature of the connecting net can be directly specified e.g. a wired or, wired and or atristated bus line, etc. In VHDL, all nets are single-source nets unless the signal driven by the net has an associated resolution function, which means every time there is an event on that net (e.g. a signal update) the resolution function has to be executed to derive the nature of that net, such as in arbitrating among multiple drivers. This puts some overhead on simulation runtime. This is a rather terse list of comments. If you requre some specific piece of information, do mail me about it. In conclusion, Verilog is a more well- defined language suited to hardware description. The power derives from its well-defined types and certain statement constructs, and the semantics is thus precise and unambiguous, which from an application-developer's point of view is great. The user is not overly restricted in the range of hardware that can be described though. The set of constructs provided can describe most if not all ASICs. In contrast VHDL is still an emerging language and the support for it has been more due to the Dod mandate rather than on its technical merits. Its power is directly dependent on the particular support given to it by the vendor - features are built upon the language rather than in it. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: Subhash Chandra Roy <roy@mcnc.org> The verilog environment will now have 2 'heads' or so our Cadence rep says. Both VHDL and Verilog will be supported. I don't recall the delievery date for the VHDL version but I remember it being around DAC. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: imken%cadillac.cad.mcc.com@mcc.com (Gary Imken) I saw your posting requesting information on a VHDL vs. Verilog comparison and thought I might pass along some information which may be helpful. My impression from talking to companies funding the MCC CAD program and those interested in joining the MCC CAD program is that VHDL has too much momentum to be ignored. The DoD mandate and the IEEE standardization mean that companies will find it increasingly difficult to justify the use of a non-standard language like Verilog, even if Verilog offers advantages over VHDL today. More and more tools are going to be written for VHDL in the future while fewer will be available for Verilog. In case you didn't know, Cadence has announced that they will be productizing the front-end of the MCC VHDL System as part of their VHDL-XL product. So within the Cadence environment, you can use either VHDL or Verilog, as you desire. VHDL-XL won't support the full IEEE 1076-1987 VHDL Standard in its first release, but if you need full VHDL support today, you might want to consider getting the MCC VHDL System. (Sales pitch => The MCC System supports the full language, has a symbolic debugging environment, and runs on a variety of workstations.) If you think you might be moving to the Cadence System in the future, the task might be a little easier if you begin using the MCC VHDL System now since a lot of the MCC code will be running in the Cadence System. If you're interested in information about the MCC VHDL System, contact Mary Inglis (phone: 512-338-3415, email: inglis@mcc.com). She can tell you about licensing the System or joining the MCC CAD program. If you have questions of a more technical nature about our implementation, also feel free to contact me (phone: 512-338-3671, email: imken@mcc.com). =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: H.-G. Zipperer <hgz@azu.informatik.uni-stuttgart.de> zipperer@informatik.uni-stuttgart.dbp.de I would like to see a summary of the responses, as we are also trying to evaluate some HDLs and design systems. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: clive@computer-science.manchester.ac.uk I would be very interested in any comments you receive. In the near future we should have access to VHDL and Verilog, but as yet I am uncertain as to which to use for our project of hardware to accelerate simulation model evaluation. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: Carson R. Stuart <carson@mcnc.org> We have not looked at all of the above issues but will be receiving Verilog shortly. The features which persuaded us were how long the tool has been around ( ~3 years), the wide use of the tool, and their support of Verilog and VHDL. I am interested in your compilation of responses. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: dona@bach Please let me know of the results. Working for an ASIC company, the results will be interesting. We already support Verilog, and we will probably start supporting VHDL very soon. (Mentor's Release 8.0 will support VHDL). =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: mpulver@adl.austek.oz.au (Mark Pulver) I can't give you any answers, because we use our own in-house language. But we had had requests from a couple of "big name" potential customers that we provide a Verilog model of our chips. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= From: mike.mcmanus@ftcollins Yes, I am interested in your feedback. Sorry, I don't have much to add myself, as I don't use these tools, but some folks I work with do, and would very interested in the responses you get. ------------------------------ END OF SIMULATION DIGEST ************************