EJS@Mit-Mc@sri-unix (09/15/82)
From: Eric J Swenson <EJS@Mit-Mc> Can anyone give me a pointer to some documentation on 6850 SIO chips? I need to be able to configure the device for 8 bit/no parity/1 stop bit and can't find any documentation on how to do it. I've sent 03H to the device which I assume reinitializes it, and then a 91H (since that is what the operating system I use does). But I'm not sure what the 91H means. I fear that the high order bit tells the device to use interrupts which I don't really want so I probably want 11H. But, can anyone tell me how to decode the bits in this command? Specifically, I need to know what to output to the control port following a reset to get the 8 bit/no parity/1 stop bit configuration. Thanks.
rconn@BRL@sri-unix (09/16/82)
From: Rick Conn <rconn@BRL>
"An Introduction to Microcomputers" Vol 2 and 3 by Os-
borne is a very good source for answers to questions such as
yours. I can really recommend it; among other things, it covers
the 8080, 8085, Z80, 6800, 6502, and other microprocessor chips
AND the support chips (6850 for ex) that can be used with these
microprocessors.
The answer to your question is in Vol 2, page 9-59: 6850
ACIA control register bits are (bit 7=high-order, bit 0=low ord-
er):
Bit 7: 0=disable receive interrupt logic
1=enable receive interrupt logic
Bits 6&5: 00=-RTS low, disable xmit interrupt logic
01=-RTS low, enable xmit int logic
10=-RTS high, disable xmit int logic
11=-RTS high, enable xmit int logic
Bits 43&2: 000=7 data bits, even parity, 2 stop bits
001=7,odd,2stop
010=7,even,1stop
011=7,odd,1stop
100=8,no parity,2stop
101=8,no,1stop
110=8,even,1stop
111=8,odd,1stop
Bits 1&0: 00=/1 clock
01=/16 clock
10=/64 clock
11=Master Reset
So, your sequence of 3H followed by 91H is:
03H = Master Reset
91H = Enable Recv Int Logic, -RTS Low & Disable
Xmit Int Logic, 8 Data Bits & No Parity & 2 Stop Bits, /16 Clock
Hope this helps.
Rick