tdl (10/19/82)
Here are a couple of random comments about the statements that Mike Meyer made about the 68000. I don't know what you mean by saying that the 68000 probably doesn't do instruction decode in "hardware". Do you mean hardware as opposed to microcode? The 68000 does have two instruction decode PLAs which generate starting addresses for the microsequences needed to implement the instruction. (Each instruction can be composed of up to 3 microsequences.) This instruction decode is always overlapped with the execution of the previous instruction; effectively, no time is spent on instruction decode. Second, the 68000 does have what Motorola calls nanocode. In early designs (speculation) they had a two level micro code similar to nanodata except that the nanorom sequences were all one cycle long. (i.e. the nanorom just does a decode of the microrom output) They patented a control structure that looks like this. I assume that they found that the feedback path from control to the datapath and back was too slow, and then came up with the current structure. The current structure looks like a two level microcode, but it's really only a one level microcode with a cute trick to save on the # of ROM bits needed. They use the same address field to address both the micro and nano ROMs. The decoder for the nanorom does not fully decode the address; therefore more than one address maps into a given word in the ROM. The micro rom contains all information on control flow while the nanorom contains all info to drive the datapath. They save bits because nanowords are not duplicated they way they would be if it was all one rom. This scheme does complicate the assignment of addresses in the microrom. (The microrom has about 550 words while the nanorom has about 350 words.) Tom Lovett houxh!tdl P.S. By the way, what is a BLT stlye Iset?