tdl (10/19/82)
This is in response to John Mathon's remarks about the 680X0.
Probably not! The instruction caching scheme in the 68010,
68020 will operate at full memory bandwidth with no wait states
meaning that all these block xxxxx instructions are pointless.
I'm not sure how much you know about the control scheme for the 68020,
but if it is even remotely related to the 68K [1] a cached block move
loop will not run at full memory bandwidth. Even given that they might
use an independent prefetch controller to fill their two word queue
(either out of the cache or out of external memory) so that the main
controller does not allocate cycles for program fetch, the move
instruction will take 4 control cycles, corresponding to the time
required for the data transfer. During the execution of the loop
insruction the bus will be idle. If the 68010 or the 68020 has a new,
heavily pipelined control scheme that you know about, I'd be
interested in hearing about it.
The big win for the 68xxx is that it
has a large linear address space and it has a relatively
orthogonal instruction set.
What does "relatively orthogonal" mean? Check out the shift
instructions for memory vs. register sources. From my point
of view the 68000 is not at all orthogonal.
Tom Lovett
Bell Labs
houxh!tdl
[1] - U.S. Patent #4,325,121, Gunter, et al. "Two-Level Control Store
for Microprogrammed Data Processor"BILLW@Sri-Kl@sri-unix (10/22/82)
From: BILLW at Sri-Kl The 68020 will have real cache memory - somewhere between 32 and 256 words worth. Only instructions will be cached (no update problems). Their goal is to improve preformance of "typical" applications 30% The 68010 is more similar to the 68000. prefecth, perhaps, but not really cache... BillW