dre@Sun.COM (David Emberson) (10/20/88)
[ This is editted due to length. Hope it is not jibberish. --- Steve ] In article <899@cps3xx.UUCP>, enbody@cpswh.cps.msu.edu (Dr Richard Enbody) writes: > > Question: ... Two characteristic of RISC processors seem to pose special > problems for this type of parallel processor .... > problems (coherence). ... If that data is being > shared with another processor, how is consistency maintained? > > What architectural support exists in current RISC processors? > What should exist? > Guesses ..... I don't see why a RISC processor's problems with consistency of register contents is any different from a CISC processor's. If you are worried about the integrity of a data structure, typically you put a semaphore around the critical section. I think you are confusing two essentially orthogonal issues: synchronization and cache consistency. Support for cache consistency and synchronization presents essentially the same set of problems regardless of one's RISC or CISC theology. Dave Emberson (dre@sun.com)