fpst@hubcap.UUCP (Steve Stevenson) (11/14/88)
You mentioned on comp.parallel that you have a 2..20 processor Unix based system. I'd like to know more about your ICN, implementation of cache coherence, synchronization primatives, and performance. Do you support a shared memory view to the users (including system programmers)? Assuming it is at least an approximate shared memory, what kind of interconnection network do you use (if shared bus, which one)? Assuming a shared bus and write-back caches, are you supporting cache coherence in hardware (if so, what protocol?) or do you leave portions of the cache coherence problem to the software (like restricting data that can be cached)? Please elaborate. What synchronization primatives do you provide in hardware? In software? What performance do you expect? Assuming a shared bus, how much bus traffic is created by the hardware primatives and your implementation of semaphores? Are there high traffic times during certain phases of the synchronization process? For example, Test-Test-and-Set causes bus transactions by every waiting processor when the lock is reset and traditional Test-and-Set always spins across the bus. You throw around some MIPs numbers like 40, 150, and 1000. Are you simply adding the power of the processors, or do you trying for an expected speedup? If it is the latter, how do you calculate it? Thanks in advance for your comments, Ross Johnson ross@cs.wisc.edu Ph.D. Student, University of Wisconsin - Madison -- Steve Stevenson fpst@hubcap.clemson.edu (aka D. E. Stevenson), fpst@prism.clemson.csnet Department of Computer Science, comp.parallel Clemson University, Clemson, SC 29634-1906 (803)656-5880.mabell