eyal%techunix.BITNET@JADE.BERKELEY.EDU (Eyal Waldman) (11/14/88)
Hello there,
I'm a student for the master degree in the Technion - Israel institute
of technology.
We've built a simulator for a Multistage Interconnection
Network (MIN) that runs on a VAX and a SUN workstation. We'd like
to test and use the simulator.
If any of you out there have one of the following:
1. Communication loads between PEs and MMs in different applications of
parallel processing. So that we'll be able to run them on our simulator
and benefit test studies for topological aspects of the MIN.
2. Simulation results that include:
- Processing Element (PE) utilization,
- average access time for a read/write operation
- number of collisions in the MIN
- or any other results
as a function of communication loads between Processing Elements (PEs)
and Memory Modules (MMs). We'll be more than glad to have these results.
If any of you have references to literature including such data please let me
know.
My E-mail address:
Domain: eyal@techunix.technion.ac.il
BITNET: eyal@techunix
UUCP: ...!psuvax1!techunix.bitnet!eyal
ARPANET: eyal%techunix.bitnet@cunyvm.cuny.edu
CSNET: eyal%techunix.bitnet@csnet-relay.csnet (last resort)
My address is:
Eyal Waldman
Electrical Eng. Dpt.
Technion city
Haifa 32000
Israel.
Thanks in advance
Eyal.