rdp@uunet.UU.NET (Ronald Pose) (11/21/88)
Ronald Pose Department of Computer Science Monash University Clayton, Victoria, 3168. AUSTRALIA Steve Stevenson or should this have gone to Barry Shein? If this should have gone elsewhere please pass it on and let me know. [!!!!!! attention !!!!!!! attention !!!!!!!!!! To Ronald and all the Non news group receivers: Send to me [ Steve Stevenson ] but address your comments to whoever the originator of the news article was. In this case, it was Barry Shein. ] I am Ronald Pose, lecturer in the Department of Computer Science at Monash University in Australia. I have been working on the architecture of a capability-based, tightly-coupled multiprocessor which has been designed and constructed at Monash University in Australia. The common communication path in the multiprocessor is a 32-bit, high-speed, synchronous multiport bus which runs at 40 MHz. This is faster than any commercially available bus driving chips can manage, so a novel bus driving scheme using discrete transistor drivers has been developed. A fast parallel bus arbitration scheme is employed together with a virtual channel bus protocol which allows our bus to have the performance of a 16x16 crossbar switch at a much lower cost. One of the aims of the project was for a system in which users take over many of the tasks traditionally left to the operating system. The system was also to be cheaply and readily extensible. A global virtual memory architecture has been implemented. In this system all entities to which users or processes can refer are objects in a single global virtual memory. There is no separate file store. Every process running on any system sharing this architecture throughout the world sees the same global virtual memory. This has great advantages in a shared memory multiprocessor since processes are logically location independent. In order to implement the global virtual memory novel address translation techniques have been devised. The central feature of the address translation scheme is the use of an Intermediate Address Space (IAS) between the logical address spaces seen in programs and the physical address space of the physical memory. The use of the IAS avoids many of the aliasing and coherency problems traditionally associated with shared memory multiprocessors. In our implementation it is the memories which do the IAS to physical address translation. The processors do the logical to IAS translation and check the access rights. This unusual split of functionality has advantages over the traditional methods and does not necessarily involve any speed penalty or any extra hardware complexity. In fact the scheme can be applied in conjunction with off-the-shelf microprocessors. Our current prototypes use NS32032 32-bit microprocessors and our own address translation hardware. Currently under development is a new faster processor based on the SPARC processor. Also under consideration are the possibilities of using AMD29000 processors and the Motorola 88000. Each of these processors have minor design difficulties which makes them awkward to use with our novel architecture. I would welcome any interest from companies making or planning fast 32-bit processors who would be interested in hearing my ideas and perhaps incorporating certain features into their products. I will be delivering a paper of mine at the 22nd Hawaii International Conference of System Sciences in Hawaii in January 1989. Late in January I will be in California for two or three weeks. I would appreciate the opportunity to discuss my system with you and I would welcome the chance to hear first hand what other research groups are doing in the area of multiprocessor computer architecture. Perhaps some joint research will be possible. You can read some more about our architecture in The Computer Journal, Vol 29, No. 1, pp.1-8, January 1986, "A Password Capability System" by Anderson, Pose and Wallace. Contacts at SUN have advised me not to bother with the first generation SPARC processors but to investigate the 2nd generation SPARCS from Fujitsu, Cypress and LSI Logic. I am also very interested in the MIPS and 88k chips. Partly our problems have been due to our unusual address translation and bus protocol schemes, but we believe that our methods are superior to the current conventional methods, are cheap and simple, and simple modifications to most of the available processor chips would make them much easier to use. If you are interested in discussing my ideas about multiprocessors and address translation schemes with me during my time in California I would be delighted to meet with your research groups and swap ideas. We would welcome assistance with our multiprocessor research and would be very interested in any research or joint development projects you might have in mind. I am willing to give talks or seminars to interested research groups. My finances will be extremely limited so I may not be able to go too far out of the main cities in California. Contact me urgently if you are interested in meeting me since I will have to organise my schedule and make arrangements. Please pass this message on to anyone who may be interested. Ronald Pose ACSnet: rdp@bruce.cs.monash.oz Dept. Computer Science UUCP: ..uunet!munnari!bruce.cs.monash.oz!rdp Monash University ARPA: rdp%bruce.cs.monash.oz.au@uunet.uu.net AUSTRALIA 3168. CSNET: rdp@bruce.cs.monash.oz.au FAX: +61 3 565 4746