SEILER@Mit-Xx@sri-unix (11/20/82)
From: Larry Seiler <SEILER@Mit-Xx> From: David A Boulton <SPAM@Mit-Ai> Subject: 6502 HCF ... Other interesting (and more subtle) problems with the 6502 include: - A Jump Indirect operation where the address is xxFF will use the bytes xxFF and xx00 instead xxFF and xxFF+1. It would have taken an extra cycle to propagate the carry, so they didn't bother. - The 6502 is claimed to prefetch instructions to improve its speed, but careful work with a logic analyser shows that while a byte may be prefetched, it is \always/ thrown away and fetched again when it is actually going to be used. - The processor has a nasty habit of reading random memory locations while it is calculating an effective address in some modes. This weird behaviour is documented by the manufacturers, but it means that you may not use indirect/ indexed modes in dealing with I/O ports since you might strobe a port twice. At least it doesn't WRITE random bytes! Overall the 6502 is not significantly worse than any other 8 bit micro, but I sure wish the designers had finished it before they started to sell them. -- spam I did a lot of work with the 6502 at one time (including using a logic analyzer to trace what it was doing), and I disagree with several of spam's statements. First, I seem to recall that the 6502 manual stated that an indirect jump with an address across a page boundary (xxFF) takes an extra cycle in order to propogate the addition. Second, the 6502 does NOT always throw away prefetched instruction bytes. That only happens on register to register instructions. For any instruction in which there is at least one data byte following the opcode byte in the instruction stream, the 6502 doesn't waste any prefetched bytes. Finally, every computer that has a cache shares with the 6502 the property of reading locations it doesn't need. All you have to do with the 6502 is avoid using a "strobe address" on an IO device as the base address of an indirect or indexed address, something that it is unlikely you'd want to do, anyway. In the PDP-11 (for example), all IO addresses have to be in a special part of memory, a greater restriction. While I'm on the subject of the 6502, someone mentioned a while ago that the 6502 doesn't have enough on-chip registers to be able to implement high level languages. What the 6502 does have is "zero page mode", which allows the first 256 memory locations to be accessed with a single byte address. Zero page instructions are just as fast as register only instructions, due to the prefetch. And if you compare microprocessor speeds based on equal memory access times, the 6502 zero page instructions are faster than 8080 or 6800 register only instructions. So in effect, the 6502 has 256 registers. Sigh. All this matters little, I suppose. Larry -------