[comp.parallel] A Taxonomy of Parallel Architectures

ben@uunet.UU.NET (Ben Lian) (12/15/88)

Can anyone point me to work on classification of parallel architectures?
I find terms like MIMD, SIMD, data parallel, etc, etc, ad nauseum, rather
unsatisfactory.  I vaguely recall Eugene Miya mentioning something about
trying to bring some sort of sense and order into such classfication, but
that was back in 1985 and it could therefore have been someone else.


Ben Lian




---------------------------------------------------------------------
Benjamin Y H Lian             ACSnet: ben@tasis.utas.oz
Dept. of EE & CS              ARPA  : ben%tasis.utas.oz.au@uunet.uu.net
University of Tasmania        BITnet: munnari!tasis.utas.oz!ben@
GPO Box 252C                          uunet.uu.net  (I think)
Hobart, Tasmania 7001         UUCP  : {enea,hplabs,mcvax,uunet,ukc}!
Australia.                            munnari!tasis.utas.oz!ben

"For every problem, there exists a solution that is simple, elegant,
and wrong."  [But why do *I* keep finding those solutions?]

jec@iuvax.cs.indiana.edu (James E. Conley) (12/16/88)

	In my architecture class we covered some other models in addition
to the Flynn model.  In particular there is the Feng, Handler, and Lipovski
models.  

	My notes are fairly sketchy, but I believe the Feng model classifies
machines by word size and number of bit-slices.  The types of machine can be
divided into (WPBS [word parallel, bit-slice serial], WSBS, WSBP, and WPBP).
You can then plot how "parallel" machines are relative to each other.

	The Handler model is an ordered set:

	T(arch) = <KxK', DxD', WxW'>

	where K is the number of processors, K' is the number of them that
are pipe-lined, D is the number of ALUs, D' is the number of them that are 
pipe-lined, W is the word size, and W' is the pipe-line depth.  The connection
machine would be:

	T(CM) = <32k x 32k, 1 x 1, 16 x 2>

	The last model is the Lipovski model and it's kind of complex.  The
idea is that it describes computing power by comparing the area of "bits
processed" times "time".  The shape of the area is supposed to give an
idea of the type of processor.   A fast but not very parallel machine will
loop like a horizontal rectangle whereas a slow but highly parallel 
architecture will look like a tall rectangle.

	Take my explanation with a grain of salt, these are from class notes
rather than any source that I've checked out myself.  If anyone has the
original references of these models, I'd be interested in seeing them.

James Conley
Indiana University Computer Science
jec@iuvax.cs.indiana.edu

eugene@eos.arc.nasa.gov (Eugene Miya) (12/16/88)

Additional taxonomies:

Hockney and Jesshope's chemistry-like notation taxonomy (advantage with numbers
but too contrived)

L. Snyder's latest ICPP 88 taxonomy (totally ignoring several of the
aforementioned).

I also believe Baer has one.

Taxonomies have very little real value except to Washington funding bureaucrats
(but perhaps I am too harsh?).

--eugene

gld@cunixd.cc.columbia.edu (Gary L Dare) (12/17/88)

In article <3904@hubcap.UUCP> Ben Lian wrote:
>Can anyone point me to work on classification of parallel architectures?
>I find terms like MIMD, SIMD, data parallel, etc, etc, ad nauseum, rather
>unsatisfactory.

The November issue of IEEE's Computer magazine has a paper by a
Waterloo professor on an extension of Flynn's taxonomy.  I didn't
give it a very deep reading, but this method just makes finer
distinctions between the basic M/SIM/SD categories for machine
structure and data storage.

gld
-- 
~~~~~~~~~~~~~~~~~~~~~~~~ je me souviens ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 Gary L. Dare                           > gld@eevlsi.ee.columbia.EDU
                                        > gld@cunixd.cc.columbia.EDU 	
 "Free Canada, Trade Mulroney!"         > gld@cunixc.BITNET

ben@uunet.UU.NET (Ben Lian) (12/19/88)

In article <3920@hubcap.UUCP> eugene@eos.arc.nasa.gov (Eugene Miya) writes:
>Additional taxonomies:
> [stuff deleted]
>Taxonomies have very little real value except to Washington funding bureaucrats
>(but perhaps I am too harsh?).


Now that's an interesting point!  What would you want a taxonomy for anyway?
Other than to say "if you show me yours, I'll show you mine".  No, only
joking.

Seriously, it would be handy to be able to describe the general characteristics
of a particular parallel machine's architecture without having to spew mouthfuls
of words containing terms/acronyms whose meanings vary depending on where you
come from, what you've read, etc.  Taxonomies such as Flynn's are now too old
and hence too general to describe the different classes of machines that have
appeared on the scene.  I'm no expert (hence my original net request) but it
also seems that there is also a lot of confusion between 'architecture' and
'programmming model'.  For example, what do YOU (indicating the plural) take
the following grab bag of terms to mean:

.  shared memory / local memory
.  processors in lock-step (systolic?) / processors asynchronous
.  data driven (i.e., dataflow) / demand driven (i.e., graph reduction)
.  data parallel
.  wavefront
.  tightly coupled
.  closely coupled
.  loosely coupled
.  distributed architecture
.  MIMD
.  SIMD
.  <add your own>

Anyway, enough said.  I don't want to prolong discussion on this topic.  I
suspect that it rears its ugly head from time to time.  There may never be
a completely satisfactory and universally acceptable way of describing parallel
architectures.  Could it be that the scene is changing so rapidly that any new
taxonomy invented is almost immediately out of date?  Someone is bound to
invent/design a new machine which can be almost, but not quite, described by
existing terms.  Hence, I think, Eugene's remark above.

Oh, BTW, Eugene Miya has threatened to 'u' comp.parallel.  Something to do
with his parallel computing bibliography.  Perhaps I can prevail on Eugene
to NOT take such a drastic action, because this newsgroup will almost
certainly miss his "gross generalizations", eh?


Ben Lian




---------------------------------------------------------------------
Benjamin Y H Lian             ACSnet: ben@tasis.utas.oz
Dept. of EE & CS              ARPA  : ben%tasis.utas.oz.au@uunet.uu.net
University of Tasmania        BITnet: munnari!tasis.utas.oz!ben@
GPO Box 252C                          uunet.uu.net  (I think)
Hobart, Tasmania 7001         UUCP  : {enea,hplabs,mcvax,uunet,ukc}!
Australia.                            munnari!tasis.utas.oz!ben

"For every problem, there exists a solution that is simple, elegant,
and wrong."  [Why do *I* keep finding those solutions?]