dgreen@CS.UCLA.EDU (Dan R. Greening) (04/13/89)
Simulated annealing is often used for combinatorial optimization and other hard problems. It uses thermodynamic properties as a metaphor for solving these problems. Simulated annealing is used for nearly every VLSI CAD problem under the sun: placement, routing, logic optimization, circuit delay. Plus some vision problems, neural network weight-setting, a huge collection of NP complete problems, etc. That's why the crossposting list is so big. I probably missed a few, too :-). I am looking for references AND people who have implemented simulated annealing applications on parallel processors. There are some difficult and interesting problems in extending simulated annealing to parallel processors. If you send parallel simulated annealing references to me via e-mail, I will compile a bibliography and share it with all contributors. I'm also interested in hearing from people who are actively WORKING in parallel simulated annealing, and will set up a mailing list if there is enough interest. Any leads you can give me to parallel simulated annealing researchers who may not read news (but have e-mail connections), would also be greatly appreciated. Please do not post a followup to this posting. There are way too many newsgroups to which this is crossposted. But please send e-mail, and we will be able to communicate among ourselves. Thanks. Dan Greening dgreen@cs.ucla.edu 213-472-4898 308 Westwood Plaza, #117 Los Angeles, CA 90024-1647