[comp.parallel] Distributed Shared Memory

jxw@rods.ius.cs.cmu.edu (John Willis) (02/27/90)

"Cache Coherence in Systems with Parallel Communication Channels and
Many Processors" is available from Philips Laboratories, 345 Scarborough
Road, Briarcliff Manor, NY 10510 as TR-88-013.  It describes a hardware/
PAL design for efficiently emulating shared-memory in the cache / memory
of a large, message-based multiprocessor using a distributed, single-ended,
linked list.

You might also keep an eye out for the Scalable Coherent Interface's
cache coherence protocol.

-John