shashank@quiche.cs.mcgill.ca (Shashank NEMAWARKAR) (08/16/90)
Hi, This is a summary of the responses received to the querry posted on the network, about the i860 compilers: |I would like to know if there exists any compiler for i860 |(research/commercial), which utilize the pipelined floating- |point load instructions (PFLD) after some analysis reveals |that it would be advantageous. Thanks to all the netters for providing the information. The replies have been edited (partially) in this summary. We hope that the contents remain the same, as in the original responses. Wilson Chan (wilson@athena.mit.edu) writes: > ... compiler for i860, there's an "optimizing" compiler from Portland, OR >that's supposed to use some of the pipeline instructions.... Steve Roy (ssr@acm.princeton.edu) writes: >To the best of my knowledge there does not currently exist a compiler >that uses ANY of the pipelined instructions. Intel has hired a >company called The Portland Group to write such a compiler and they >say it will be in beta by the end of the year. > >Given past intel performance, don't hold your breath. We're not. >We've got a 32 node hypercube based on the i860 and we've been writing >custom assembly language libraries to get any speed at all out of the >thing. Rob Kurver (rob@dutncp8.tudelft.nl) writes: >The Metaware compiler Intel provides with their StarBase evaluation >system does not use pfld, not dual instruction mode. The Portland >Group (an Oregon, USA based company) claims to do better code >generation, including dual instruction mode and possibly pipelined >loads - as I haven't actually used their compiler yet I can't be >more specific. > >Because commercially available compilers don't seem to be doing a very >good job here, we have decided to write a post-optimizer that will read >in, optimize and write back a COFF executable. This optimizer will do > - instruction scheduling (dual instruction mode, dual operation > mode, delayed branching etc.); > - pipelining (pipelined load, but also pipelined FPU instructions); > - and more. >The optimizations will be tuned for our particular needs. Rene Rehmann (rehmann@iam.unibe.ch) writes: >The only project I know of is a developement of Meiko (and Hypersoft) for their >i860 board. Hypersoft is developing a C++ compiler and Meiko is doing the >front-end for it. Paul Puglia (puglia@cucevx.civil.columbia.edu) writes: > ..I work with a group that is using i860... the current compilers > for the chip are do not do it justice. Ramaraj Srinivasan (ramaraj@cdacb.ernet.in) writes: >There are no research/commercial compilers that automatically generate >PFLD instructions for i860. However, there is a (vectorizer !?) tool >called VAST-2 (vector and array syntax translator) for Fortran from Pacific >Sierra Research Corporation, Placerville, California. The Fortran compiler >used is from Green Hills inc. This tool VAST-2 is a pre-processor which >takes the sequential fortran program and generates calls to vector libraries >(that come along with VAST-2) when loops of certain forms are recognized. >this is a source to source translator. these translated fortran programs >are then compiled using green-hill's compiler and run. >that is the only tool i know for i860, now. Alan S. Mazer (alan@elroy.Jpl.Nasa.Gov) writes: >This has been discussed at length lately on the net, but one that comes to >mind is that of The Portland Group. It's just now being released. Their >phone number is (503) 682-2806. This seems to be the most advanced i860 >compiler on the market and the only one that takes advantage of the pipeline >that I know of. Actually, Alliant is also supposed to have such a compiler, >but I don't think the compiler is available apart from the machine at the >moment. Alan had conducted a similar survey, the summary of which was forwarded to us by Heng Chu ( chu@cs.unc.edu): > ... >There was an article on comp.arch. It's >not directly related to your question, but I believe it's a good pointer. > ... > >> survey article << > > >There appear to be four compilers out there: > >1. The "default" Intel compiler developed by Green Hills software. >2. The MetaWare compiler. >3. A GNU C compiler. >4. The one from The Portland Group. > >The Green Hills compiler is available now, but is, according to everyone >who mentioned it, horrible. People around here who have used it have said >that their code on the i860 runs about as quickly as on the 68030. Hardly >conclusive, but a data point. (I don't know what algorithms they were >running.) > >The MetaWare compiler works, but is not smart enough to get anywhere near >peak performance out of the chip. One MetaWare user who replied suggested >assembly language if you want to get even half the advertised speed. > >All I heard about the GNU C compiler is that it exists. I don't know if >it's available. It does not make real use of the architecture, but it >does generate correct code and perform normal optimizations. > >The Portland Group is Intel's newest friend. This compiler does make use >of i860 pipelining, but it's a new offering and the literature is a little >vague. Perhaps all the interesting information is proprietary. The >compiler itself is reportedly available now, and the assembler and linker >will be available "in 10 days". One person speculated that ultimate >performance using this compiler might be around 10-20 Mflops. > >I think we'll wait until someone shows us a board/compiler combination that >works reasonably on our algorithms. CSPI and The Portland Group are getting >together, so that might not be too long. > >-- Alan Robert Ellefson (bobeson@saturn.ucsc.edu) writes: >... >So far, we know about: > >The Portland Group, which does do pfld, haven't seen it, though, >Metware, no pfld, >Intel, terrible, not released, >FSF, GNU compiler with broken back-end. The response from a Metaware personnel is: >We are currently the official C and Pascal compilers shipped by >Intel on its i860 systems. We are under contract by Intel to >develop use of pipelined floating point. We currently do a lot >of scheduling, but are now starting to do true dependency analysis >for software pipelining. > ... >these compilers will probably be available by the end of this calendar >year. An Intel personnel writes: >Regarding your question if any compilers are using the pfld instruction >of the i860, yes, just about all the current compilers generate that >instruction. The lone exception maybe the GCC compiler. The others >are: Green Hills, MetaWare, Alliant, AT&T, The Portland Group, >Compass, etc. just to name a few. On further querries, he responded: >I can only talk about compilers that I have access to here within >Intel. ... >it is harder for me to tell what is "commercially" available >to users on the outside. ... I have seen >code generated by compilers from the vendors mentioned that contained >pipeline code, but then again, the compilers may not yet be >available outside. The response from Compass is: >COMPASS is releasing a version of our i860 compiler featuring improved >execution speed by means of software pipelining and the use of the dual >instruction mode in the foreseeable future. More information about our >product and related work is available from Director of Marketing Louis >Zand at (617) 245-9540. >From above responses we feel that: 1- with possible exception of the Portland group, no commercially available compiler supports the pipelined instructions. Two netters have indicated the availability of such compilers in near future. 2- it has taken a long time for the software vendors to come up with the effective usage of the PFLD. As responses from industry have indicated, the compilers utilizing the pipeline instructions are at some stage of development at many facilities. 3- few efforts have been in the directions of writing own code to effectively utilize the features provided by the chip. Any comments on the survey would be welcome Shashank Nemawarkar Herbert Hum ----------------------------------------------------------------------