delgado@bingvaxu.cc.binghamton.edu (Jose Delgado) (08/22/90)
International Workshop on
VLSI FOR ARTIFICIAL INTELLIGENCE AND NEURAL NETWORKS
University of Oxford -- September 5-7, 1990
___________________________________________________________________
Research on architectures dedicated to artificial intelligence (AI)
processing has been increasing in recent years, since conventional
data or numerically oriented architectures are not able to provide
the computational power and/or functionality required. For the
time being these architectures have to be implemented in VLSI
technology with its inherent constraints on speed, connectivity,
fabrication yield and power. This in turn impacts on the
effectiveness of the computer architecture.
The aim of this second workshop on VLSI for AI and Neural Networks
is again to provide a forum where AI experts, VLSI and Computer
Architecture designers can come together to discuss the present
status and future trends on VLSI and ULSI implementations of
machines for AI computing. This workshop will be held in an
informal environment with poster and regular session along with
time for impromptu discussions.
To encourage interaction, the workshop will be limited to a maximum
of 70 participants. The workshop sessions, meals and accommodation
will all be provided in the unique atmosphere of Jesus College
between the evening of the 4th September and lunchtime on the 7th
September 1990. The college was founded in 1571 by Queen Elizabeth
I; meals will be taken in the traditional medieval hall, a perfect
setting for the Conference Dinner on the Thursday evening.
SPONSORS
The Workshop is organised by the University of Oxford Department
for External Studies in conjunction with the Department of
Engineering Science and the Department of Electrical Engineering at
SUNY-Binghamton. The workshop is sponsored by the University of
Oxford in association with SUNY Binghamton, ACM-SIGARCH and the IEE.
PROGRAMME COMMITTEE
Igor Aleksander, Imperial College London (UK)
Howard Card, University of Manitoba (Canada)
Jose Delgado-Frias, SUNY-Binghamton (USA)
Richard Frost, University of Windsor (Canada)
Peter Kogge, IBM (USA)
Will Moore, Oxford University (UK)
Alan Murray, University of Edinburgh (UK)
John Oldfield, Syracuse University (USA)
Lionel Tarassenko, Oxford University (UK)
Philip Treleaven, University College London (UK)
Benjamin Wah, University of Illinois (USA)
Michel Weinfield, Ecole Polytechnique (France)
ENQUIRES
Registration:
Ms. Anna Morris (VLSI for AI & NN)
CPD Unit, Department for External Studies,
University of Oxford,
Rewley House, 1 Wellington Square,
OXFORD OX1 2JA, England.
Tel.: +44 865 270360 Fax: +44 865 270708
Technical queries to:
Dr. Jose G. Delgado-Frias
Dept. of Electrical Engineering
State University of New York at Binghamton
Binghamton, NY 13901 USA
Tel.: (607)777 4806 or 4856
Email: delgado@bingvaxu.cc.binghamton.edu
(or) delgado@bingvaxa.bitnet
or Dr. Will Moore,
Department of Engineering Science,
University of Oxford,
Parks Road, OXFORD, OX1 3PJ, England.
Tel.: +44 865 273187 (or 273000)
Telex: 83295G Fax: +44 865 273010
Email: moore@vax.ox.ac.uk (not available via uupc).
BACKGROUND
The workshop, organised by the University of Oxford Department for
External Studies in conjunction with the Department of Engineering
Science, is the seventh in an occasional series on topics in VLSI
and follows the successful workshop on VLSI for Artificial
Intelligence at Oxford in 1988.
FEES
Standard fee 345 (pounds) to cover accommodation (nights of Sept.
4-6); all meals from supper on Sept. 4 to lunch on
Sept. 7 (including Workshop dinner); a copy of the
preprints; a copy of the edited proceedings when
published; and a visit to the "Oxford Story".
No-room fee 275 (pounds) to cover lunches, daytime refreshments,
Workshop dinner; a copy of the preprints; a copy of
the edited proceedings when published; and a visit
to the "Oxford Story".
------------R E G I S T R A T I O N---------------------
U N I V E R S I T Y O F O X F O R D
Continuing Professional Development Programme
REGISTRATION FORM
COURSE TITLE: Int. Workshop on VLSI for Artificial Intelligence & Neural Nets
DATES: September 5-7, 1990
Please reserve places on the course for the following people
1 TITLE __________________ NAME _______________________________________
JOB TITLE _______________________________________
VEGETARIAN: Yes / No
COMPANY / ORGANIZATION _______________________________________________
ADDRESS ______________________________________________________________
______________________________________________________________
POSTCODE _____________________ TELEPHONE______________________________
FEES: _____________ (pounds) SIGNATURE___________________________
(Cheques should be made payable to O.U.D.E.S.)
------------------------end of registration form--------------------
* P R O G R A M M E *
* P R O G R A M M E *
Wednesday September 5th, 1990
8.30-9.00am Registration
9.00-10.45am INTRODUCTION
Will Moore, University of Oxford
Session A: PULSE STREAM AND BIOLOGICALLY-BASED NEURAL NETS
Chairman: Howard Card, University of Manitoba
A1 "Computational Capabilities of Biologically-realistic
Analog Processing Elements"
C. Fields, M. DeYong, and R. Findley
New Mexico State University, USA
A2 "Results from Pulse-stream VLSI Neural Network Devices"
Michael J. Brownlow, Lionel Tarassenko, Alan F. Murray
Oxford University / Edinburgh University, UK
A3 "Working Analogue Pulse Stream Neural Network Chips"
Alister Hamilton, Alan F. Murray, H. Martin Reekie and
Lionel Tarassenko
Edinburgh University / Oxford University, UK
10.45-11.15am Coffee
11.15-12.45pm Session B: DIGITAL IMPLEMENTATIONS OF NEURAL NETWORKS
Chairman: Michel Weinfield, Ecole Politechnique
B1 "The VLSI Implementation of the 'sigma' Architecture"
S. R. Williams and J. G. Cleary
University of Calgary, Canada
B2 "A Cascadable VLSI Architecture for the Realization
of Large Binary Associative Networks"
Werner Poechmuller and Manfred Glesner
Technische Hochschule Darmstadt, Germany
B3 "Digital VLSI Implementations of an Associative
Memory Based on Neural Networks"
Ulrich Ruckert, Christian Kleerbaum and Karl Goser
University of Dortmund, Germany
12.50-2.00pm Lunch
2.15-4.00pm Session C: HARDWARE SUPPORT FOR AI
Chairman: Jose Delgado-Frias, SUNY-Binghamton
C1 "Incremental Garbage Collection Scheme in KL1
and its Architectural Support of PIM"
Yasunori Kimura, Takashi Chikayama, Tsuyoshi
Shinogi, and Atsuhiro Goto
Fujitsu Laboratories/ICOT, Japan
C2 "COLIBRI: A Coprocessor for Lisp based on RISC"
H Hafer, J Plankl, F J Schmitt
Siemens AG, Germany
C3 "A CAM Based Architecture for Production System Matching"
Pratibha and P. Dasiewicz
University of Waterloo, Canada
C4 "SIMD Parallelism for Symbolic Mapping"
C.J. Wang and S.H. Lavington
University of Essex, UK
4.00-4.30pm Tea
4.30-6.00pm Session D: PARALLEL MACHINES FOR PROLOG
Chairman: Peter Kogge, IBM
D1 "SYMBOL: A Parallel Incremental Architecture
for Prolog Program Execution"
A. De Gloria, P. Faraboschi, E. Guidetti
University of Genoa, Italy
D2 "Architectural Considerations for Achieving
High Performance Prolog Execution"
Mark A. Friedman and Gurindar Sohi
University of Wisconsin, USA
D3 "A Prolog Abstract Machine for Content-Addressable Memory"
Hamid Bacha
Coherent Research, Inc., USA
Thursday September 6th, 1990
9.00-10.45am Session E: ARCHITECTURES FOR ARTIFICIAL INTELLIGENCE
Chairman: Will Moore, Oxford University
E1 "VLSI Design of a 3-D Highly Parallel Message-Passing
Architecture"
J-L Bechennec, C. Chanussot, V. Neri, and D. Etiemble
Universite de Paris-Sud, France
E2 "Embedded Processor for Realtime AI and NN Applications"
Robert T. Wang, John M. Walsh, and Ron Everett
Integrated Inference Machines, USA
E3 "Architectural Design of the Rewrite Rule
Machine Ensemble"
Hitoshi Aida, Sany Leinwand and Jose Mesaguer
SRI International, USA
E4 "A Dataflow Architecture for AI"
Jose G. Delgado-Frias, Ardsher Ahmed, and Robert Payne
SUNY-Binghamton, USA
10.45-11.15am Coffee
11.15-12.45pm Session F: ANALOGUE IMPLEMENTATIONS OF NEURAL NETWORKS
Chairman: Lionel Tarassenko, Oxford University
F1 "Analog VLSI Models of Mean Field Networks"
Christian Schneider and Howard Card
University of Manitoba, Canada
F2 "An Analogue Neuron Suitable for a Data Frame Architecture"
W A J Waller, D L Bisset and P M Daniell
University of Kent, UK
F3 "A Class of Optimal-Analog Parallel Computer
Architectures for AI"
Jonathan W. Mills
Indiana University, USA
F4 "Fully Cascadable Analogue Synapses Using
Distributed Feedback"
Donald J. Baxter, Alan F. Murray, and Martin Reekie
University of Edinburgh, UK
12.50-2.00pm Lunch
2.15-4.00pm Session G: POSTER SESSION
4.00-4.30pm Tea
4.30-6.00pm Session H: IMPLEMENTATION AND APPLICATIONS OF NEURAL NETWORKS
Chairman: Dan Hammerstrom, Adaptive Solutions, Inc.
H1 "Efficient Implementation of Massive Neural Networks"
James Austin, Tom Jackson and Alan Wood
University of York, UK
H2 "A Fully Digital Neural Network Chip Using
Probability Coding"
John Shawe-Taylor, Pete Jeavons, and Max Van Daalen
University of London, UK
H3 "Parallel Analogue Computation for Real-time Path Planning"
Lionel Tarassenko and Gillian Marshall
Oxford University, UK
7.00pm Reception and Conference Dinner
Friday September 7th, 1990
9.00-10.45am Session I: ARRAYS FOR NEURAL NETWORKS
Chairman: Alan Murray, University of Edinburgh
I1 "A Highly Parallel Digital Architecture for
Neural Network Emulation"
Dan Hammerstrom
Adaptive Solutions, Inc., USA
I2 "Systolic Method for Modelling Spatio-Temporal
Properties of Neurons using Domain Decomposition"
Arno J Klassen and Rob Wiers
Delft University of Technology, The
Netherlands
I3 "A Delay-Insensitive Neural Network Engine"
C D Nielsen, J Staunstrup and S R Jones
Technical University of Denmark, Denmark
I4 "A VLSI Implementation of Multi-layered Neural
Networks: 2-Performances"
Bernard Faure and Guy Mazare
IMAG, France
10.45-11.15am Coffee
11.15-12.45pm Session J: UNI-PROCESSOR MACHINES FOR PROLOG
Chairman: Simon Lavington, University of Essex
J1 "An Extended Prolog Instruction Set for RISC Processors"
Andreas Krall
University of Vienna, Austria
J2 "A VLSI Engine for Structured Logic Programming"
P L Civera, E Lamma, P Mello, A Natali, G L
Piccinini, and M Zamboni
Politecnico di Torino, Italy
J3 "Performance Evaluation of a VLSI Associative
Unifier in a WAM Based Environment"
P L Civera, G Masera, G L Piccinini, M Ruo
Roch and M Zamboni
Politecnico di Torino, Italy
-- P O S T E R S --
G1 "Binary Neural Network with Delayed Synapses"
Tadashi Ae, Yasuhiro Mitsui, and Reiji Aibara
Hiroshima University, Japan
G2 "Implementing Neural Networks with the Associative String Processor"
A. Krikelis and M. Groezinger
Aspex Microsystems Ltd., UK
G3 "Syntactic Neural Networks in VLSI"
Simon Lucas and Bob Damper
University of Southampton, UK
G4 "Massively Parallel Neural Network Architecture for the Solution of
Linear Equations Based on the Hopfield Network"
J. R. Minick and M. A. Styblinski
Texas A&M University, USA
G5 "A New Architectural Approach for Flexible Digital Neural Network
Chip Systems"
Torben Markussen
Technical University of Denmark, Denmark
G6 "Systolic Architecture for a Subquadratic Converging Neural Network
Learning Algorithm"
Philippe De Wilde
Imperial College of Science and Technology, UK
G7 "A VLSI Implementation of a Generic Systolic Synaptic Building
Block for Neural Networks"
Christian Lehmann and Francois Blayo
Ecole Polytechnique Federale de Lausanne, Switzerland
G8 "A Learning Circuit that Operates by Discrete Means"
W P Cockshott and G Milne
University of Strathclyde, UK
G9 "A Compact and Fast Silicon Implementation for Layered Neural Networks"
F. Distante, M. G. Sami, R. Stefanelli, G. Storti-Gajani
Polytechnic of Milan, Italy
G10 "Pulse-Firing VLSI Neural Circuits for Fast Image Recognition"
S. Churcher, A. F. Murray and H. M. Reekie
University of Edinburgh, UK
G11 "The ULM - A RISC for Lisp"
Reinhard Rasche
Technical University of Berlin, Germany
G12 "Logic Flow in Active Data"
Peter Sapaty
Ukranian Academic of Sciences, USSR
G13 "A Multi-Transputer Architecture for a Parallel Logic Machine"
M. Cannataro, G. Spezzano and D. Talia
CRAI, Italy