tbridg@iuvax.cs.indiana.edu (Tim Bridges) (09/03/90)
Interconnection Topology Survey
I am conducting a survey of the largest instantiations of various
interconnection topologies. This work is part of an attempt to analyze
scalability factors for parallel architectures. If you can provide a candidate
architecture that may provide the largest example of any of the listed
topologies, please respond with the size description and a reference to:
tbridg@iuvax.cs.indiana.edu
As an example, I would submit the following:
Hypercube - 4096 nodes (12 dimension), CM-2, Thinking Machines Corp.,
and a reference to a TMC technical report or Hillis' book. This system
has actually been implemented.
There may be bigger hypercube architectures built or proposed. If so, I would
like to hear from someone out there.
I am solliciting entries for the following connection topologies. If you have
a submission that doesn't fit one of these categories, please submit and give
a description. This list is not meant to be exhaustive. No constraint is made
as to SIMD or MIMD systems. I am attempting to collect data on physical
systems as well as proposed systems. If in doubt, submit and provide
descriptive text.
Bus - # of processors
2-D Grid
Hypercube
Omega or Banyon
Crossbar
Tree
In addition, I would like to hear about the biggest (# of words) RAM
implementations on uni-processor and shared memory multi-processor systems.
This data provides a good baseline.
Thank you in advance for your help. I will, of course, summarize and post
the survey results.
Timothy Bridges
tbridg@iuvax.cs.indiana.edu