eugene@wilbur.nas.nasa.gov (Eugene N. Miya) (09/08/90)
Dr. David Kahaner is a numerical analyst visiting Japan for two-years
under the aspice of the Office of Naval Research-Far East (ONRFE).
The following is the professional opinion of David Kahaner
and in no way has the blessing of the US Government or any agency of it.
[DKK]
Back issues of most reports will shortly be available via anonymous FTP.
Host is pending. [ENM]
To: Distribution
From: David Kahaner ONRFE
Re: Parallel processing meeting, July 1990
6 September 1990
The Japanese Institute of Electronics, Information and Communications
Engineers (IEICE) and the Japanese Information Processing Society held a
joint meeting July 18-20 1990 on parallel processing. Meeting conflicts
prevented my attending. We have now prepared a list of the papers and
their authors from the Proceedings. Most of the papers were presented in
Japanese. A few are in English and these are so noted. Readers of my
reports will notice that a number of the papers present material that I
have discussed earlier. I have visited some of the other reserachers,
including those of the OSCAR, HARRAY, and CAP projects and will report on
them later. Many of the papers represented research that I was not aware
of until now.
For copies of the complete Proceedings or information about individual
papers please write to IEICE at the following address. For queries to me
or to IEICE it is best to refer to papers by number, CPSY 90-12, etc.
The Institute of Electronics, Information and Communications Engineers
Kikai-Shinko-Kaikan Bldg.
508 Shibaokoen 3 chome, Minato-ku
Tokyo 105, JAPAN
THE INSTITUTE OF ELECTRONICS,
INFORMATION AND COMMUNICATION ENGINEERS (IEICE)
TECHNICAL REPORTS
CPSY 90 - 12 - 37
[COMPUTER SYSTEMS]
July 19-20, 1990
Prepared by Office of Naval Research
Liaison Office, Far East
Dr. David K. Kahaner
APO San Francisco 96503-0007
IEICE TECHNICAL REPORTS
CPSY 90-12, through 90-37
Table of Contents
Mutual Networks..........................CPSY 90-12 - 14
Basic/Language...........................CPSY 90-15 - 17
Applications.............................CPSY 90-18 - 21
Compiler.................................CPSY 90-22 - 25
Analysis/Evaluation......................CPSY 90-26 - 28
Image Processing.........................CPSY 90-29 - 31
Scheduling...............................CPSY 90-32 - 34
Shared Resources MIMD/Dataflow...........CPSY 90-35 - 37
Database.................................CPSY 90-38 - 40
Integration/Deadlock Detection...........CPSY 90-41 - 42
Architecture.............................CPSY 90-43 - 45
Load Distribution........................CPSY 90-46 - 48
OS.......................................CPSY 90-49 - 52
Fine Grained/Superscalar Processor.......CPSY 90-53 - 55
Pattern Recognition/Neural Network.......CPSY 90-56 - 59
Graphics.................................CPSY 90-60 - 63
JAPAN INFORMATION PROCESSING SOCIETY MACHINE ARCHITECTURE STUDY REPORTS
90 - ARC - 83-1 through 83-40
Table of Contents
1A: Program Generation\Verification............................83-1 - 3
1B: Applications...............................................83-4 - 6
1C: Compiler...................................................83-7 - 9
1D: Architecture.............................................83-10 - 12
2A: Algorithm................................................83-13 - 15
2B: Scheduling...............................................83-16 - 18
2C: Cache....................................................83-19 - 21
2D: Development\Environment Evaluation.......................83-22 - 24
3A: OS.......................................................83-25 - 28
3B: VLIW.....................................................83-29 - 32
3C: GC/Debug Environment.....................................83-33 - 36
3D: CAP-II...................................................83-37 - 40
Mutual Networks
CPSY 90-12 Algorithms for Asynchronous Operation in an Omega Network
with the Flat Bucket Distribution Mechanism
Yasushi Ogawa (Research and Development Center,
Ricoh Co., Ltd.)
Masaru Kitsuregawa (Institute of Industrial Science,
University of Tokyo)
90-13 Performance Evaluation of Various Networks Embedded on
Prodigy Highly Parallel Computer
Noboru Tanabe, Sadao Nakamura, Shigeru Oyanagi
(Research & Development Center, Toshiba Corp.)
90-14 Multiplexed Crossbar Network of the Kyushu University
Reconfigurable Parallel Processor and Its Floor Plans
Shinichiro Mori, Kazuaki Murakami, Akira Fukuda,
Shinji Tomita (Interdisciplinary Graduate School of
Engineering Sciences, Kyushu University)
Basic/Language
90-15 Parallel Object-Oriented Programming Feature in Valid
Shigeru Kusakabe, Takashi Tomokiyo, Rinichiro
Taniguchi, Makoto Amamiya (Graduate School of Engineering
Sciences, Kyushu University)
90-16 On Structural Properties of Computation Determinacy and
Token Self-Cleanness of Data-Flow Program Nets (in English)
Qi-Wei Ge, Toshimasa Watanabe, Kenji Onaga
(Faculty of Engineering, Hiroshima University)
90-17 A Thought on Cooperative Computation (in English)
Norihiko Yoshida (Kyushu University)
Applications
90-18 Computer System Based on Japanese
Katsumi Osuga, Kazuo Kurokawa (Science University of Tokyo)
90-19 Parallel Sort on a Multiprocessor Workstation
Takeo Nakada (IBM Research, Tokyo Research
Laboratory, IBM Japan, Ltd.)
Susumu Horiguchi (Department of Information
Engineering, Tohoku University)
90-20 An OR Parallel Execution Scheme of Prolog on Loosely
Coupled Multiprocessor Systems
Morikazu Nakamura, Seiki Kyan (University of the
Ryukyus) Tsuyoshi Kawaguchi (Miyazaki University)
90-21 Evaluation of Hierarchical Pincers Attack Search for
Parallel Processing of Prolog on NCUBE2
Munenori Kai (Seikei University)
Compilers
90-22 An Implementation of Linda System on a Shared Memory
Multiprocessor
Y. Kimura, S. Sumimoto, A. Hosoi, T. Ozawa, A.
Hattori (Artificial Intelligence Laboratory, Fujitsu
Laboratories Ltd.)
90-23 Statical Allocation of a Modularized Flow Graph
Shigeyoshi Nakajima, Jiro Okamoto, Kazumi
Yamashita (Faculty of Engineering, Osaka City Univ)
Kiyotsugu Satoh (College of Industrial Technology)
90-24 A Macro-block Controlling Scheme of Parallel Processing
System -Harray -
Hayato Yamana, Toshiaki Yasue, Jun Kohdate,
Yoichi Muraoka (School of Science and Engineering,
Waseda University)
90-25 A Fortran Compiler for Parallel Processing System - Harray
Toshiaki Yasue, Jun Kohdate, Hayato Yamana, Yoichi
Muraoka (School of Science and Engineering, Waseda Univ)
Analysis/Evaluation
90-26 Approximate Analysis of Memory Contention in Tightly
Coupled Multiprocessor Systems
Takashige Hoshiai (NTT Communication Switching Labs)
90-27 Access Delay Characteristics of Buffered Multistage
Interconnection Networks for Multiprocessor Systems - An
Approximated Analysis
Leo Nagamatsu, Koichiro Deguchi, Iwao Morishita
(Faculty of Engineering, University of Tokyo)
Toshiki Kizu (Toshiba Corp)
90-28 State-of-the-art in Performance Evaluation Techniques for
Parallel Supercomputers
Satoshi Sekiguchi (Electrotechnical Lab)
Image Processing
90-29 Implementation and Evaluation of a Parallel Computer
System with 256 Floating Point DSP's
Masaki Kohata, Taku Ito, Yoshiya Miyagaki (Okayama
University of Science)
90-30 Parallel DSP System for Super High Definition Image
Processing Tetsurou Fujii, Tomoko Sawabe, Naohisa
Ohta, Sadayasu Ono (NTT Transmission Systems Labs)
90-31 The Architecture and Efficiency of RIPE: A Real-time Image
Processing Engine (in English)
Masaharu Imai, Kunio Honsawa, Nobuhiko Yamada, Jota Tomita,
Jun Sato (Dept of Information and Computer Sciences,
Toyohashi University of Technology)
Junichi Hasegawa (Department of Liberal Arts, Chukyo
University)
Scheduling
90-32 A Task Allocation Strategy for Parallel Computers
Takanobu Baba, Tsutomu Yoshinaga (Faculty of
Engineering, Utsunomiya University)
Yoshifumi Iwamoto (Consultant)
90-33 On Real-time Distributed Scheduling Problem in
Distributed Systems (in English)
Issam A. Hamid, Setsuo Ohsuga (Research Center
for Advanced Science and Technology, University of Tokyo)
90-34 Task Allocation Algorithm Based on an Exclusiveness
Between Two Tasks
Shinya Kobayashi, Hikaru Nakanishi, Yoshikazu
Tezuka (Faculty of Engineering, Osaka University)
Yoshio Komaki (Canon)
Shared Resources MIMD/Dataflow
90-35 The Implementation and Evaluation of a Cyclic Pipeline
Computer FLATS2
Shuichi Ichikawa (Research Development
Corporation of Japan) Eiichi Goto (Faculty of
Science, University of Tokyo)
90-36 Performance Evaluation Through Simulation of a
Multistage-Network Shared-Memory Parallel Machine with
Multi-Instruction-Stream Processors
Yoshiaki Sudo, Leo Nagamatsu, Koichiro Deguchi,
Iwao Morishita (Faculty of Engineering, University of Tokyo)
Kazuya Tago (IMB Research, Tokyo Research Lab.,
IBM Japan, Ltd.)
90-37 Implementation of Color Management Scheme on Data Driven Computer
Yoshihiko Ishii, Toshiaki Yasue, Hayato Yamana, Yoichi
Muraoka (School of Science and Engineering, Waseda
University)
Database
90-38 Design of Effective Backup Schemata for Main Memory
Database Systems
Hiroki Takakura (Faculty of Engineering, Kyushu
University) Yahiko Kambayashi (Faculty of
Engineering, Kyoto University)
90-39 Software of SDC, The Super Database Computer
Satoshi Hirano, Masanobu Harada, Minoru Nakamura,
Weikang Yang, Masaru Kitsuregawa, Mikio Takagi
(Institute of Industrial Science, University of Tokyo)
90-40 Concurrency Control for Parallel Transactions
Keizo Saisho (Faculty of Engineering, Kyushu
University) Yahiko Kambayashi (Faculty of
Engineering, Kyoto University)
Integration/Deadlock Detection
90-41 A Survey of Ada Tasking Deadlock Detection Methods (in
English) Jingde Cheng (Dept of Computer Science
and Communication Engineering, Kyushu University)
90-42 A Mechanism for Integrating Communication and
Synchronization using Snoopy Cache
Takashi Matsumoto, Tomoyuki Tanaka, Takao Moriyama,
Shigeru Uzuhara (IBM Research, Tokyo Research Lab)
Architecture
90-43 Voting Fault Tolerant Arrays
Hideki Mori, Junichi Kamubara, Akira Kubo, Shigehisa
Komatsu, Toshiya Ajita, Minoru Niimura (Dept of Information
and Computer Sciences, Faculty of Engineering, University of
Tokyo)
90-44 The Architecture of the Inference Unit of Parallel Inference
Engine PIE64
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
(Faculty of Engineering, University of Tokyo)
90-45 Processor Element's Architecture for a Missively Parallel
Computer System
Hiroaki Fujii, Haruo Niimi, Kiyoshi Shibayama
(Dept of Information Science, Kyoto University)
Load Distribution
90-46 The Parallel Solution of Classification Problems (in English)
Hirotoshi Maegawa (Knowledge Systems Lab, Dept of
Computer Science, Stanford University, USA; Corporate
Research Labs, Sony Corp., Japan)
90-47 Load Balancing Methods in a Highly Parallel Dataflow Machine
EM-4
Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
(Electrotechnical Lab)
90-48 KL1 Parallel Execution on Shared Memory Multi-Processor -
Load Balancing and Unification
Akira Imai, Atsuhiro Goto (Institute for New
Generation Computer Technology (ICOT))
Yoshiyuki Doumae (Fujitsu Social Science Lab, Ltd.)
OS
90-49 Multilanguage Communication and Persistent Object Access
in the XERO Omnigenous Operating System
Kazuhiko Kato, Shigeru Chiba, Shigekazu Inohara,
Takashi Masuda (Dept of Information Science, Faculty of
Science, University of Tokyo)
90-50 A Study of Communication Primitives in a Distributed System
Junichi Taniguchi, Takashige Hoshiai, Kogiku Ichizo
(NTT Communications Switching Labs)
90-51 Persistent Caching Algorithm on Distributed Environment
Toshio Tonouchi, Kazuhiko Kato, Takashi Masuda
(Dept of Information Science, Faculty of Science,
University of Tokyo)
90-52 An Approach for Distributed File Management Systems
Tetsuo Hasegawa, Toshibumi Seki, Yasukuni
Okataku, Shinsuke Tamura (Systems & Software
Engineering Lab., Toshiba Corp.)
Fine Grained/Superscalar Processor
90-53 A Fine Grained Parallel Architecture for Effective Execution of
Conditional Structure
Eishun Suzuki, Yoshiaki Fukazawa, Toshio Kadokura
(School of Science and Engineering, Waseda University)
Hideaki Komatsu (Tokyo Research Lab., IBM Japan, Ltd.)
90-54 An Extended Superscalar Processor Prototype Based on the SIMP
(Single Instruction Stream/Multiple Instruction Pipelining)
Architecture
Kazuaki Murakami, Morihiro Kuga, Shinji Tomita
(Interdisciplinary Graduate School of Engineering
Sciences, Kyushu University)
90-55 Organizations of An Extended Superscalar Processor Prototype
Based on the SIMP (Single Instruction Stream/Multiple Instruction
Pipelining) Architecture
Tetsuya Hara, Akira Nodomi, Morihiro Kuga,
Kazuaki Murakami, Shinji Tomita (Interdisciplinary
Graduate School of Engineering Sciences, Kyushu
University)
Pattern Recognition/Neural Network
90-56 On Parallel Processing for On-line Handwritten Kanji Recognition
by Hypothesis Setting
Kenji Ohmori (Dept of Industrial Engineering and
Systems Engineering, Faculty of Engineering, Hosei
University)
90-57 Systolic Architecture for Character/Speech Recognition System
Hirotomo Aso, Shinichiro Ohmachi, Masayuki Kimura
(Faculty of Engineering, Tohoku University)
Yutaka Katsuyama (Fujitsu Ltd.)
90-58 A Formal Model for Neural Computation
Kaoru Nakazono (NTT Basic Research Labs)
90-59 Neural Network Models on SIMD Architecture Parallel Computer
Makoto Hirayama (ATR Auditory and Visual
Perception Research Labs)
Graphics
90-60 A Parallel Visualization Software for Cellular Array Processor
CAP-II
Hiroyuki Sato, Hiroaki Ishihata (Fujitsu Labs, Ltd.)
Hajime Namikata (Nagaoka University of Technology)
90-61 Parallel Processing of a 3-D Display Obtained from
Medical Images
Noboru Niki, Yoshiki Kawata (Faculty of Engineering,
Tokushima University)
90-62 Display Processor
Nobuyuki Moriya, Yasushi Wauke, Takayoshi Yoshida,
Ikuo Oyake (Systems Lab., Oki Electric Ind. Co., Ltd.)
90-63 A Load Balancing Method for Rendering
Kazutaka Nishio, Kenji Nishimura, Jiro Minehisa,
Makoto Hirai, Yoshimori Nakase (Kansai Information &
Communications Research Lab., Matsushita Electric Ind.
Co., Ltd.)
INFORMATION PROCESSING SOCIETY STUDY REPORTS
July 18, 1990
1A: Program Generating/Verification
83-1 On Parallel Theorem Prover for Temporal Logic
Kazunori Matsumoto, Shinichi Honiden (Systems & Software Lab.,
Toshiba Corp)
83-2 Design Philosophy of Advanced Environment for Software Production: AESOP
Hiroaki Nishikawa, Hiroaki Terada (Dept of Information
Systems Engineering, Faculty of Engineering, Osaka Univ)
Shinichi Yoshida, Souichi Miyata (IC Engineering Center,
Sharp Corp.)
Shunji Hine, Masahiro Noguchi (Kansai Information and
Communications Research Lab., Matsushita Electric Ind. Co., Ltd.)
Youichiro Nishikawa, Shuji Hara (Information & Communication
Systems Research Center, Sanyo Electric Co., Ltd.)
Kenji Shima, Shoichi Washino (Industrial Electronics & Systems
Development Lab., Mitsubishi Electric Corp.)
83-3 A Prototype of the Diagrammatical Specification Environment AESOP
Youichiro Nishikawa, Shuji Hara (Sanyo Electric Co., Ltd.)
Yoshie Inaoka, Tetsuo Yamasaki, Kenji Shima (Mitsubishi Electric
Corp.)
Shinichi Yoshida (Sharp Corp.)
Shunji Hine (Matsushita Electric Ind. Co., Ltd.)
Hiroaki Nishikawa, Hiroaki Terada (Osaka Univ)
1B: Applications
83-4 Parallel Computation of a Multidimensional Fast Fourier Transform on a
Binary Tree Multiprocessor
Noboru Niki, Yasunori Tomikawa (Faculty of Engineering,
Tokushima Univ)
83-5 Automatic Test Pattern Generation using Parallel Processing System
Takashi Minohara, Yoichiro Ueno, Kenji Konatsu, Yoshihiro
Tohma (Dept. of Computer Science, Tokyo Institute of Technology)
83-6 Solution of Fluid Dynamics on TOP-1
Gyo Ohsawa (IBM Research, Tokyo Research Lab., IBM Japan, Ltd.)
1C: Compiler
83-7 LISP-Compilation Toward Supercomputing with Large Granularity
Masaaki Fukase (Research Institute of Electrical Communication,
Tohoku Univ)
Tadao Nakamura (Dept of Mechanical Engineering, Faculty of
Engineering, Tohoku Univ)
83-8 A Study on Design Support for GHC Program
Akira Honjo, Shunsuke Nakajima (Oki Telecommunication Systems
Co., Ltd.)
Haruo Hasegawa (Oki Electric Ind. Co., Ltd.)
Ryuzo Hasegawa (Institute for New Generation Computer Tech)
83-9 Program Partitioning Algorithms for a Parallel Processing System
Hideaki Murata, Shinya Kobayashi, Hikaru Nakanishi, Yoshikazu
Tezuka (Faculty of Engineering, Osaka Univ)
1D: Architecture
83-10 Sparse-Matrix Processor Based on Content Addressable Memory
Koichi Sato, Kazuto Kubota, Tatsuo Ohtsuki (School of
Science and Engineering, Waseda Univ)
Masao Sato (Faculty of Engineering, Takushoku Univ)
83-11 A Virtual Shared Memory System on Ring-Connected Parallel Computer
Hironori Nakajo, Yukio Kaneda (Dept of Systems
Engineering, Faculty of Engineering, Kobe Univ)
Koichi Wada (Institute of Information Science and Electronics,
Univ of Tsukuba)
83-12 A Highly Parallel Architecture Using Ring-Register Data Way
Hideki Yoshizawa, Hideki Kato, Hiroki Ichiki, Kazuo
Asakawa (Computer-Based Systems Lab., Fujitsu Labs. Ltd.)
2A: Algorithm
83-13 An LU Decomposition Algorithm for Parallel Supercomputers
Yoshiki Seo, Naoki Nishi (C&C Systems Research Labs., NEC
Corp.) Yukimasa Shiroto (NEC Scientif Info System Development)
83-14 Linear-Time MCC Algorithms for Some Geometrical Problems
Akinobu Kawamura, Hiroshi Umeo (Osaka Electro-
Communication Univ) Takashi Ishikawa (Matsushita Soft
Research, Inc.)
83-15 Parallel Processing Scheme of the Solution of Stiff Nonlinear Ordinary
Differential Algebraic Equations on OSCAR (in English)
Wichian Premchaiswadi, Hiroki Honda, Hironori Kasahara,
Seinosuke Narita (Dept of Electrical Engineering, Waseda Univ)
2B: Scheduling
83-16 Parallelized Optimizing Multiprocessor Scheduling Algorithm
Hironori Kasahara, Hisamitsu Tanaka, Keisuke Itoh (School of
Science and Engineering, Waseda Univ)
83-17 Parallel Processing of Near Fine Grain Tasks on OSCAR (Optimally
Scheduled Advanced Multiprocessor)
Hironori Kasahara, Hiroki Honda, Wichian Premchaiswadi,
Akio Ogura, Akiyoshi Mogi, Seinosuke Narita (Dept of
Electrical Engineering, Waseda Univ)
83-18 A Multiprocessor Resource Management Scheme which Considers Program
Grain Size
Takao Moriyama, Yasushi Negishi, Shigeru Uzuhara, Takashi
Matsumoto (IBM Research, Tokyo Research Lab., IBM Japan, Ltd.)
2C: Cache
83-19 Performance Simulation of a Multi-Level Cache/Bus Architecture
Hirofumi Muratani (Toshiba R&D Center, Info and System Lab.)
83-20 Proposal of a Revalidating-type Multi-chache Consistency Protocol and
its Evaluation
Kazumasa Hamaguchi, Shigeki Shibayama (Information Systems
Research Center, Canon Inc.)
83-21 Integrated Parallelizing Compiler System - Compiler-Assisted Cache
Coherence Scheme
Eiji Iwata, Shinichiro Mori, Kazuaki Murakami, Akira Fukuda,
Shinji Tomita (Dept of Information Systems, Interdisciplinary
Graduate School of Engineering Sciences, Kyushu Univ)
2D: Development/Environment Evaluation
83-22 Parallel Software Simulator of Cellular Array Processor CAP-II
Morio Ikesaka, Takeshi Horie (Fujitsu Labs., Ltd.)
83-23 Developing Environments and Implementation Techniques for Parallel
Language Processor - For Example: KL1 Processor in PIM
Tsuneyoshi Takagi, Reki Yamamoto, Akira Imai (Institute
for New Generation Computer Technology), Akihiko Nakase
(Toshiba Corp.)
Kiyoshi Hirano, Yasuyuki Nakagoshi (Fujitsu Social Science Lab.)
83-24 Performance Measurement Environment of a Multiprocessor Workstation
TOP-1
Nobuyuki Ohba, Moriyoshi Ohara, Hisa Yamasaki, Shigenori
Shimizu (IBM Research, Tokyo Research Lab., IBM Japan, Ltd.)
3A: OS
83-25 Multiprocessor Operating System: SKY-1 - Thread Interface
Masahiko Saitoh, Tadashi Kamiwaki, Shinichiro Yamaguchi
(Hitachi Research Lab., Hitachi, Ltd.)
83-26 An Operating System "OS/omicron" for Parallel and Distributed
Processing
Mitarow Namiki, Hiroyuki Okano, Takashi Yokozeki, Nobumasa
Takahashi (Dept of Computer Science, Tokyo Univ of Agriculture
and Technology)
83-27 Memory Management of Multiprocessor UNIK "MUSTARD"
Katsutoshi Nihei, Shunichi Hiroya (C&C Common Software
Development Lab., NEC Corp.)
Hiromi Kawaguchi (NEC Scientific Information System Development
Ltd.)
83-28 Implementation and Evaluation of a Parallel Operating System
Yasuichi Nakayama, Koichiro Deguchi, Iwao Morishita (University
of Tokyo), Kazuya Tago (Tokyo Research Lab., IBM Japan, Ltd.)
3B: VLIW
83-29 Performance of the C Compiler for VLIW Computer KIDOCH
Masato Abe (Computer Center, Tohoku Univ)
Satoshi Hongo (Faculty of Engineering, Tohoku Univ)
Keniti Kido (Chiba Institute of Technology)
83-30 Multiple VLIW Processor Architecture: Prometheus
Hideki Sunahara (Dept of Computer Science, The Univ of Electro-
Communications)
83-31 A VLIW Architecture for Optimal Design of Dedicated System
Tetsuya Tomonaka (ATRC Mitsubishi Heavy Ind., Ltd.)
83-32 A Proposal on Fuzzy Computer Hardware Architecture
Hidekazu Tokunaga, Atushi Katumata, Sozo Yamamoto, Yoshifumi
Inoue, Seiji Yasunobu (Lab for International Fuzzy Engineering
Research)
3C: GC/Debug
83-33 Multiwindow Debugger Hyper DEBU and its Control Mechanism for Parallel
Programs
Junichi Tatemura, Hanpei Koike, Hidehiko Tanaka (Faculty of
Engineering, The University of Tokyo)
83-34 The Structure of the Inference Engine Embedded in "mimsy", the Test
Debugging Environment for Parallel Programs
Tsuyoshi Yamada, Hiroyoshi Ohara (School of Science and
Engineering, Waseda Univ)
83-35 A Parallel Garbage Collector on a Shared-Memory Multiprocessor
Shigeru Uzuhara (IBM Research, Tokyo Research Lab.)
83-36 A Real Time Garbage Collection Method for Distributed Memory Parallel
Computers
Hanpei Koike, Hidehiko Tanaka (Faculty of Engineering,
the Univ of Tokyo)
3D: CAP-II
83-37 An Architecture of Highly Parallel Processor CAP-II
Hiroaki Ishihata, Satoshi Inano, Takeshi Horie, Toshiyuki
Shimizu, Sadayuki Kato (Fujitsu Labs, Ltd.)
83-38 Routing Controller of Cellular Array Processor CAP-II
Takeshi Horie, Morio Ikesaka, Hiroyuki Ishihata (Fujitsu
Labs, Ltd.)
83-39 Broadcast-network of Highly Parallel Processor CAP-II
Sadayuki Kato, Toshiyuki Shimizu, Takeshi Horie, Hiroaki
Ishihata (Fujitsu Labs, Ltd.)
83-40 A Message Controller for a Highly Parallel Processor, CAP-II
Toshiyuki Shimizu, Hiroaki Ishihata, Takeshi Horie
(Fujitsu Labs, Ltd.)
--------------END OF REPORT---------------------------------