lin@csvax.seas.smu.edu (11/07/90)
================================================================= THE SECOND IEEE SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING Sponsored by: IEEE Computer Society IEEE - Dallas Chapter In Cooperation with: Southern Methodist University University of Texas at Dallas December 9-13, 1990 -- Colony Parke Hotel, Dallas, Texas This symposium provides a forum for the presentation and exchange of current work on a wide variety of topics in parallel and distributed processing including: - Computer Architecture - Programming Languages - Data- & Knowledge-bases - AI Technologies - Operating Systems - Parallel Algorithms - Neural Network - Computer Applications - Network & Communication - VLSI System Design - Graphics - Simulation TUTORIALS: T1: Dec. 9: Future of Supercomputing - Next Decade & Beyond, Stephen Lundstrom, PARSA. T2: Dec. 9: The Workstation/Server Model of Distributed Computing, Milan Milenkovic, IBM. T3: Dec. 13: Parallel/Distributed Architectures for Data/Knowledge Based Systems, Ali R. Hurson, Pennsylvania State University T4: Dec. 13: Distributed Database Operating Systems: Architectures and Issues in Integration, M. Tamer Ozsu, University of Alberta. HOTEL RESERVATIONS: Please place your reservations directly with Colony Parke Hotel, 6060 North Central Expressway, Dallas, TX 75206, tel.: 800-527-1808, in Texas call 800-441-9258. You must mention the symposium (SPDP) in order to receive the special symposium rates ($54/night - single room, $64/night - double room). Reservations should be made before November 25, 90. After this date, reservations are subject to availability. PLEASE SEND REGISTRATION FORM AND PAYMENT TO: Dr. Sajal K. Das, Department of Computer Science, P.O. Box 13886, University of North Texas, Denton, TX 76203. Tel (817)565-4256, FAX (817)565-2599. Symposium or Tutorial Fees: (Advance Registration: Before 11/25/90) IEEE Members...............(Advance US$140, On-site US$170) Non-IEEE Members...........(Advance US$175, On-site US$220) Students...................(Advance US$60, On-site US$75) IEEE No.:__________________________________ Symposium:______ Tutorial: ______, Specify choice of tutorial(s):________ Total: ______ ___Check or bank draft enclosed (payable to SPDP) ___Credit Card (VISA or Master Card ONLY) VISA No.:___________________________ Master Card No.:________________________ Expiration Date:____________________ _______________________________________________________ Last Name First Name Initial _______________________________________________________ Organization _______________________________________________________ Address _______________________________________________________ City, State, Zip/Country _______________________________________________________ Telephone _______________________________________________________ E-mail address ======================================================================= Second IEEE Symposium on Parallel and Distributed Processing Colony Parke Hotel, Dallas, Texas December 9-13, 1990 Advance Program Tutorials Sunday, December 9, University Park T1: The Future of Supercomputing - The Next Decade and Beyond Stephen F. Lundstrom, PARSA Important multidisciplinary applications are driving the development of new scientific supercomputing capabilities toward the teraflop range. This course will look at the facts of where available technologies are now, how they are advancing, and how they might be used to implement the future of fully scaled teraflop computing systems. Sunday, December 9, White Rock T2: The Workstation/Server Model of Distributed Computing Milan Milenkovic, IBM An in-depth analysis of fundamental concepts and design techniques of distributed systems, with special emphasis on the workstation/server model of distributed computing, are presented. Topics include: algorithms, fault tolerance, naming, process migration, remote procedure calls, distributed file systems, server and client design issues (stateful vs. stateless, client caching). Illustrations of important points are drawn from contemporary implementations such as Andrew and Sprite. Thursday, December 13, University Park T3: Parallel/Distributed Architectures for Data/Knowledge Based Systems Ali R. Hurson, Pennsylvania State University The proliferation of data combined with higher performance requirements have forced designers of data/knowledge based systems to look beyond software solutions. This tutorial overviews some of the new developments in centralized and distributed environments. In addition, it covers the hardware- software implementation of these issues. Special attention will be paid to the relational data model and data/knowledge based machines. Finally, a survey of current research and interest in this area will be addressed. Thursday, December 13, White Rock T4: Distributed Database Operating Systems: Architectures and Issues in Integration M. Tamer Ozsu, University of Alberta This tutorial addresses the technical issues that need to be solved and the architectural models that can be used to better integrate distributed database managers and distributed operating systems. The emphasis is on distributed DBMS requirements for operating system services. The technical issues that require further research are identified. Various distributed operating system architectural models are analyzed with respect to their suitability for supporting distributed DBMS functions. Technical Program Note: l = long paper (22 min.), s = short paper (12 min.) Monday, December 10, 8:30-10:00 AM Welcoming Remarks, Behrooz Shirazi, UT-Arlington Keynote Speech: Developing Complex, Distributed, Real-Time Systems Raymond T. Yeh, SYSCORP International This Talk will discuss a new process and integrated system to support the development of real-time embedded systems. The alternative process will allow overlapping development phases with concurrent activities to deal with frequent requirements changes and use prototypes as key mechanisms to access high risk factors. An integrated environment to support this process will be discussed. The cornerstones of such a system engineering environment includes flexible graphic user interface, specification compiler, reuse at various levels, and rapid prototyping at different levels of design. Monday, December 10, 10:00-10:30 AM Break, Poster Presentation I Monday, December 10, 10:30 AM-12:00 N North Ballroom: Algorithms I Chair: Ioannis Tollis, UT-Dallas l: A Fast NC Algorithm to Recognize P4-Sparse Graphs R. Lin, SUNY at Geneseo and S. Olariu, Old Dominion Univ. l: The Maximum Weight Perfect Matching Problem for Complete Weighted Graphs in PC Constantine Osiakwan and S.G. Akl, Queen's University l: Energy Complexity of Optical Computations Akhilesh Tyagi and John Reif, Univ. of North Carolina s: LR-Heap: A Concurrent Implementation of Priority Queues Rassul Ayani, The Royal Institute of Technology s: Parallel Algorithms for Optimal Ranking of Trees Y. Liang, S.K. Dhall, and S. Lakshmivarahan, University of Oklahoma South Ballroom: Task Scheduling I Chair: Gideon Frieder, Syracuse University l: Decentralized Decision Making in Adaptive Task Sharing Hemant G. Rotithor and S.S. Pyo, Worcester Polytechnic Institute l: Dynamic-Level Scheduling for Heterogeneous Processor Networks Gilbert C. Sih and Edward A. Lee, University of California, Berkeley l: Deterministic Load Balancing in Computer Networks Xiaotie Deng, Stanford Univ., Hai-Ning Liu, and Bing Xiao, Univ. of California at San Diego s: Dynamic Load-Balancing on a Parallel Inference System Zhiyong Liu and Jia-Huai You, University of Alberta s: Algorithms for End-to-End Scheduling to Meet Deadlines Riccardo Bettati and Jane W.S. Liu, Univ. of Illinois at Urbana- Champaign West Ballroom: Networks I Chair: S. Lakshmivarahan, University of Oklahoma l: Composite Routing Protocols Anish Arora, Mohamed Gouda, and Ted Herman, University of Texas at Austin l: Topology of Efficiently Controllable Banyan Multistage Networks Abdou Youssef and Bruce Arden, George Washington Univ. l: Subcube Recognition, Allocation/deallocation and Relocation in Hypercubes Mee-yee Chan and Shiang-jen Lee s: An Average-Case Algorithm for Routing Permutations on a MESH Interconnection Network Jop F. Sibeyn, University of Utrecht s: A Simulation-Based Comparison of Interconnection Networks M.T. Raghunath and Abhiram G. Ranade, University of California, Berkeley Monday, December 10, 12:00-1:30 PM Lunch Break Monday, December 10, 1:30-3:00 PM North Ballroom, Panel I Supercomputer Technology Trends Organizer, Moderator: Steve Wallach, Convex Computers Inc. South Ballroom, Operating Systems I Chair: Milan Milenkovic, IBM l: Execution Replay on Distributed Memory Architectures Eric Leu, Andre Schiper, and Abdelwahab Zramdini, Ecole Polytechnique Federale de Lausanne l: Divide and Conquer for Distributed Mutual Exclusion K.V.S. Ramarao, SBC Technology Resources Inc. and K. Brahmadathan, Univ. of Wyoming s: The ServOS Kernel: A Special-Purpose OS Kernel for Server Machines Stefan Schleipfer, InterFace Computer GmbH s: A Correct Two-Phase Deadlock Detection Algorithm for Distributed Systems Ajay D. Kshemkalyani and Mukesh Singhal, Ohio State University s: Barrier Synchronization over Multistage Interconnection Networks Craig A. Lee, The Aerospace Corporation West Ballroom, Databases Chair: Margaret Eich, Southern Methodist University l: A New Paradigm for High Availability & Efficiency in Replicated Distributed Databases Peter Triantafillou and David Taylor, University of Waterloo l: Parallel Join Processing Using Non-clustered Indexes for a Shared Memory Multiprocessor Edward Omiecinski and Ron Shonkwiler, Georgia Institute of Technology s: Main Memory Database Recovery Algorithms and Their Performance Vijay Kumar and Albert Burger, University of Missouri-Kansas City s: A Crash Recovery Algorithm Based on Multiple Logs that Exploits Parallelism Akhil Kumar, Cornell University s: A Transaction Definition Based on Message Passing Francisco Mariategui and Margaret H. Eich, Southern Methodist Univ. Monday, December 10, 3:00-3:30 PM Break, Poster Presentation II Monday, December 10, 3:30-5:00 PM North Ballroom: Architecture I Chair: Krishna Kavi, UT-Arlington l: Design of Optimal Systolic Arrays: A Systematic Approach M.O. Esonu, A.J. Al-Khalili, Concordia Univ., and S. Hariri, Syracuse Univ. l: A Broadcast/reduce Architecture for High-speed Data Compression Roland Zito-wolf, Brandeis Univ. l: Multiple Instruction Streams in a Highly Pipelined Processor Mitsuhisa Sato, Shuichi Ichikawa, Research Development Corporation of Japan (JRDC), and Eiichi Goto, Univ. of Tokyo s: High-Speed Propagation of Link Status Routing Control Information Douglas Comer, Purdue Univ., and Rajendra Yavatkar, Univ. of Kentucky s: Deterministic Simulation of PRAMs on Hypercube Networks Without Look-up Tables Todd Heywood, Arif Ghafoor, and Jim K. Chan, Syracuse University South Ballroom, Fault Tolerance I Chair: Bill Carroll, UT-Arlington l: Evaluation & Improvement of Fault Coverage for Verification & Validation of Protocols Y.-N. Shen and Fabrizio Lombardi, Texas A&M University l: Distributed, Dynamic, & Efficient Testing of Large Scale Multiple Processor Systems Seyed H. Hosseini and N. Jamal, Univ. of Wisconsin--Milwaukee l: Fault Tolerant Distributed Computing Using Atomic Send-Receive Checkpoints Zbigniew M. Wojcik and Barbara E. Wojcik, Univ. of Texas at San Antonio s: An Effective Fault-Tolerant Technique for Circular Butterfly Parallel Systems Nian-Feng Tzeng, University of Southwestern Louisiana s: Real-Time Tasks Redundancy Management Anne-Marie Deplanche, Ecole Nationale Superieure de Mecaniq. West Ballroom, Algorithms II Chair: Vijaya Ramachandran, UT-Austin l: Parallel Execution of Lanczos Algorithm in a CAM Systolic Ring C. Ko, Rutgers University l: Optimistic Regulation of Concurrency Arch D. Robison, Univ. of Illinois at Urbana-Champaign l: An Asymptotically 100% Efficient Parallel Implementation of the Nonsymmetric QR Algorithm Duncan G. Hudson, iii and Robert A. Van de Geijn, Univ. of Texas at Austin s: Integer Sorting on a Mesh-connected Array of Processors Danny Krizanc, Univ. of Rochester s: Time Complexity of a Heuristic Algorithm for the k-Center Problem with Usage Weights Qingzhow Wang and Kam-Hoi Cheng, University of Houston Monday, December 10, 6:00-9:00 PM Social Hour, Cash Bar, 6:00-7:00 PM Symposium Dinner, 7:00-9:00 PM Tuesday, December 11, 8:30-10:00 AM North Ballroom, VLSI Design Chair: A.R. Hurson, Penn State University l: A Parallel Architecture for Data Compression Selwyn Henriques and N. Ranganathan, University of South Florida l: Allowing Overlaps Makes Switchbox Layouts Nice Michael Kaufmann, Univ. des Saarlandes s: Multi-Level VLSI Simulator For General Purpose Parallel Machines E. Aposporidis and F. Lohnert, Daimler-Benz AG s: Parallel Algorithms for Slicing Floorplan Designs Cheng-hsi Chen and Ioannis G. Tollis, Univ. of Texas at Dallas s: A Parallel Distributed Processing Approach to VLSI Global Routing John Provence, Southern Methodist Univ., and S. Naganathan, Texas Instruments South Ballroom, Algorithms III Chair, S.K. Dhall, University of Oklahoma l: Convergence/response Tradeoffs in Concurrent Systems Mohamed G. Gouda and Michael Evangelist, Univ. of Texas at Austin l: An Optimal Parallel Minimax Tree Algorithm David G. Kirkpatrick and Teresa Przytycka, Univ. of British Columbia l: Approximation Algorithms for the Bandwidth Minimization Problem for Caterpillar Graphs James Haralambides, Fillia Makedon, and B. Monien, Univ. of Texas at Dallas s: Analysis of Parallel Algorithms Using Continuous Job Profiles Mason L. Weems, Nasr Ullah, Mario J. Gonzalez, jr, Univ. of Texas at Austin s: Packing Flexible Rectangles into a Two Dimensional Bin Jiahuang Ji, University of Houston West Ballroom, Architecture II Chair: Akshay K. Deshpande, AT&T l: An Adaptive Cache Coherence Scheme for Hierarchical Shared-Memory Multiprocessors Qing Yang, G. Thangadurai, Univ. of Rhode Island, and Laxmi N. Bhuyan, Texas A&M Univ. l: Distributed Input/Output Processing in Data-Driven Multiprocessors Paraskevas Evripidou, Southern Methodist Univ., and Jean-Luc Gaudiot, Univ. of Southern California s: Design of a Highly Parallel IEEE Standard Floating Point Unit: The Cyrix 83D87 Coprocessor David W. Matula, Southern Methodist Univ. s: A Universal On-line Bit-Serial Cell for Parallel Expression Evaluation Soren Peter Johansen, Odense Universitet s: European Declarative System (EDS) Machine Kam-fai Wong, ECRC Gmbh Tuesday, December 11, 10:00-10:30 AM Break, Poster Presentation III Tuesday, December 11, 10:30 AM-12:00 N North Ballroom, Potpourri Chair, John Feo, Lawrence Livermore Lab. s: Parallel Join Algorithms for Nested Relations on Shared-Memory Multiprocessors Vinay Deshpande, P.-A. Larson, Univ. of Waterloo, and T.P. Martin, Queen's University s: A High Performance Hybrid Architecture for Concurrent Query Execution Kien A. Hua, Chiang Lee, IBM- Mid-Hudson Laboratories, and Jih- Kwon Peir, IBM T. J. Watson Research Center s: Type Inference and the Algebra of Qualified Relations David Eichmann, West Virginia University s: The Application of Parallel Processing to the Simplified Marker and Cell Method David B. Johnson, Peter E. Raad, and Randall E. Rausch, Southern Methodist Univ. s: Systolizing Compilation Michael Barnett, Univ. of Texas at Austin s: Design of the PRAM Network Jonathan Sandberg, Princeton Univ. s: Modeling Distributed Termination with Pre-defined Partial Termination Ordering T. Elrad, N.K. Kumar, and J.R. Kenevan, Illinois Institute of Technology South Ballroom, Task Scheduling II Chair: Girish Pathak, Xerox l: Scheduling in Operation-Oriented Paradigm A. Sayed Muhammed Sajeev, Massey University l: Optimal Partitioning of Random Workloads in Homogeneous Multiprocessor and Distributed Systems Emile K. Haddad, Virginia Polytechnic Inst. & St. Univ. l: Scheduling Tasks with AND/OR Precedence Constraints Donald W. Gillies and Jane W.-S. Liu, Univ. of Illinois at Urbana-Champaign s: Dynamic Load Balancing for Parallel Program Execution on a Message-passing Supercomputer Jian Xu s: Scheduling Precedence Graphs to Minimize Total System Time in Partitionable Parallel Architectures Hyeong-Ah Choi and B. Narahari, George Washington Univ. West Ballroom, Graphics/Image Processing Chair: Robert Bechtel, Merit Technology l: Termination Condition for a Parallel Shape Coding Zbigniew M. Wojcik and Barbara E. Wojcik, Univ. of Texas at San Antonio l: Binary Representation and Surface Interpolation of the Grey Level Image by Relaxation Neural Network Models Noboru Sonehara, Advanced Telecom. Research Inst. Intl. l: A Parallel Distributed Algorithm for Feature Extraction and Display Robert J. Schalkoff and M.S. Mousavi, Clemson University s: Recognition and Restoration of Periodic Patterns with Recurrent Neural Network Ryotaro Kamimura, Tokai University s: Efficient Parallel Execution of Neighborhood Operations on an SIMD Machine De-lei Lee, York Univ., and Wayne A. Davis, Univ. of Alberta Tuesday, December 11, 12:00-1:30 PM Lunch Break Tuesday, December 11, 1:30-3:00 PM North Ballroom, Panel II Resolved: RPC is a Mediocre Distributed Programming Facility Organizer and Moderator: E. Douglas Jensen, Concurrent Computer Corp. South Ballroom, Artificial Intelligence Chair: Said Bettayeb, Louisiana State University l: Accelerated Learning on the Connection Machine Diane J. Cook and Lawrence B. Holder, Univ. of Illinois at Urbana-Champaign l: Forward Chaining Parallel Inference Michael C. Rowe, Jay Labhart, Robert Bechtel, Merit Technology Inc., Steve Matney, and Steve Carrow, Naval Research Laboratory l: Parallel Execution on Production Systems Fu-Chiung Cheng, Huei-Huang Chen, and Jiin-Hwai Perng, Tatung Inst. of Technology s: Extended Restricted And-Parallelism Execution Model Si-En Chang, Mark L. Manwaring, Washington State Univ., and Y. Paul Chiang, Texas Instruments s: Parallel Path Planning in the Presence of Obstacles Erwin Prabler and Evangelos Milios, Research Institute for Applied Knowledge Processing West Ballroom, Algorithms IV Chair: Kam-Hoi Cheng, University of Houston l: An Efficient Algorithm for Multi-process Shared Events Vijay Kumar Garg and Sandeep Ajmani, Univ. of Texas at Austin l: An Efficient Parallel Algorithm for Solving Set Recurrence Equations and Applications Oscar H. Ibarra, Tao Jiang, and Hui Wang, Univ. of California, Santa Barbara l: Parallel Algorithms for Determining K-width-connectivity in Binary Images Frank Dehne and Susanne E. Hambrusch, Purdue Univ. s: Parallel Dynamic Programming Venkatraman Viswanathan, Shou-Hsuan Stephen Huang, and Hongfei Liu, Univ. of Houston s: Parallel Bin Packing Using First-fit and K-delayed Best-fit Heuristics Azer Bestavros and William McKeeman, Harvard University Tuesday, December 11, 3:00-3:30 PM Break, Poster Presentation IV Tuesday, December 11, 3:30-5:00 PM North Ballroom, Panel III Future Trends in High Performance Arithmetic: Chips, Boards, and Supercomputers Organizer and Moderator: David Matula, Southern Methodist University South Ballroom, Fault Tolerance II Chair: Nian-Feng Tzeng, University of Southwestern Louisiana l: Randomized Fault-Detecting Leader Election in a Bi-Directional Ring Neal R. Wagner, University of Texas at San Antonio l: Multi-Failure Fault-Tolerance of Embedded Loops on Hypercubes: Issues and Performance Study C.T. Liang and W.S. Tsai, University of Minnesota s: On the Testability of Array Structures for FFT Computation Fabrizio Lombardi, Texas A&M Univ. and J. Muzio, Univ. of Victoria s: A Software Approach to Fault Detection on Systolic Shared Register Machines Richard Hughey and Daniel Lopresti, Brown University s: Self-Testing and Self-Reconfiguration Architecture for 2-D WSI Arrays Hussam Y. Abujbara and Sami A. Al-Arian, University of South Florida West Ballroom, Networks II Chair: Laxmi Bhuyan, Texas A&M University l: A Topological Property of Hypercubes: Node Disjoint Paths Seshu Madhavapeddy and I. Hal Sudborough, Univ. of Texas at Dallas l: Embedding of Cycles and Grids in Star Graphs Jung-Sing Jwo, S. Lakshmivarahan, and S.K. Dhall, University of Oklahoma s: Improving Multistage Interconnection Network Performance Under Uniform and Hot-Spot Traffics Jih-Kwon Peir, IBM T.J. Watson Research Center, and Yann-Hang Lee, Univ. of Florida s: Computer Network Reliability Evaluation from Application's Point of view Anup Kumar, Univ. of Louisville, and Dharma P. Agrawal, North Carolina State Univ. s: Efficient Routing and Conflict Resolution in F and IADM Networks K.C. Anand, Tata Inst. of Fundamental Research, Dharma P. Agrawal, and Nita M. Kini, North Carolina State Univ. Wednesday, December 12, 8:30-10:00 AM North Ballroom, Task Scheduling III Chair: James Abello, Texas A&M University l: A Semi Distributed Load Balancing Scheme for Large Multicomputer Systems Ishfaq Ahmad and Arif Ghafoor, Syracuse University l: Analysis and Synthesis of Generalized Task Graphs Krishna Kant, Pennsylvania State University l: An Optimal Algorithm for Guaranteeing Sporadic Tasks in Hard Real-time Systems M. Silly, H. Chetto, and N. Elyounsi, Ecole Nationale Superieure de Mecaniq. s: Self Scheduling and Execution Threads R.S. Francis and A.N. Pears, Latrobe Univ. s: Average Response Time Minimization in Star-connected Computer Networks G.R. Dattatreya and R. Venkatesh, Univ. of Texas at Dallas South Ballroom, Languages/Compilers Chair: Rischiyur Nikhil, MIT l: A Strict Monolithic Array Constructor Guang R. Gao, Robert Kim Yates, McGill University, Jack B. Dennis, MIT, and R. Mullin, Univ. of Vermont l: The Complexity of Processing Tree Queries in Distributed Databases Chihping Wang, University of California at Riverside s: SISAL 1.2: High-Performance Applicative Computing David Cann, John T. Feo, and Thomas M. DeBoni, Lawrence Livermore Lab. s: Multiprocessor Common Lisp on TOP-1 Tomoyuki Tanaka and Shigeru Uzuhara, IBM, Tokyo Research Laboratory s: Multiple Concurrency Control Policies in an Object-Oriented Programming System Gail E. Kaiser, Wenwey Hseush, Steven S. Popovich, and Shyhtsun F. Wu, Columbia University West Ballroom, Algorithms V Chair: Eliezer Dekel l: LU Factorization on CM2 Shan Jiang, Syracuse University l: Using Universe Knowledge and Arithmetic to Get Faster Parallel Algorithms Vassilis J. Tsotras, B. Gopinath, and George W. Hart, Columbia Univ. s: An Improved Parallel Algorithm for Constructing Voronoi Diagram on a Mesh-Connected Computer Chang-sung Jeong, Pohang Institute of Science & Tech. s: Synthesis of Simple Distributed Detection Networks Nageswara Rao, Old Dominion University s: Multi-version Memory: Software Cache Management for Concurrent B-trees William E. Weihl and Paul Wang, MIT Wednesday, December 12, 10:00-10:30 AM Break, Poster Presentation V Wednesday, December 12, 10:30 AM-12:00 N North Ballroom, Operating Systems II Chair: Mary Lou Soffa, University of Pittsburg l: RDS: A Primitive for the Maintenance of Replicated Data Objects Marek Rusinkiewicz, Dimitrios Georgakopoulos, and Roshan Thomas, Univ. of Houston l: A General RPC for Model-Level Heterogeneous RPC Interoperability Alex Stoyenko, IBM T.J. Watson Research Center l: Solving the Processor Identity Problem in O(n) Space Lloyd Lim and Arvin Park, Univ. of California, Davis s: Efficient Caching of Temporary Files Ignacio Valdes and Jehan-F. Paris, University of Houston s: Variations on the Drinking Philosophers Algorithms S.E. Chern, R.T. Jacob, and I.P. Page, Univ. of Texas at Dallas South Ballroom, Fault Tolerance III Chair: Prasenjit Biswas, Texas Instruments l: On the Fault Diagnosis of a VLSI Cellular Array Tsair-Chin Lin, Cadence Design Systems, Inc., and Hsing Mei, Univ. of Texas at Arlington l: Transparent Structurization of Parallel Processes for Backward Recovery A.B. Romanonsky and I.V. Sturtz, Leningrad Polytechnical Institute l: fault-tolerant Computing on Trees Ajit Agrawal, Brown Univ. s: Recovery with Limited Replay: Fault-tolerant Processes in Linda Srikanth Kambhatla and Jonathan Walpole, Oregon Graduate Institute s: Fault Tolerant Distributed Shared Memory Algorithms Michael Stumm and Songnian Zhou, Univ. of Toronto West Ballroom, Architecture III Chair: Paraskevas Evripidou, Southern Methodist University l: Datarol: A Massively Parallel Machine Architecture for Functional Languages Makoto Amamiya and Rin-ichiro Taniguchi, Kyushu University l: A Virtual Bus Architecture for Dynamic Parallel Processing K.C. Lee s: Rapid Design of Testable, High-Performance/ Capacity Associative Memories A.R. Hurson and P.M. Miller, Pennsylvania State University s: Restructuring Wafers for Maximum Yield, and Some Applications of WSI Dinesh Bhatia, Univ. of Texas at Dallas s: Context Streams - A Theoretical Basis For a Generic Form of MIMD Pipelining Timothy Lees, Univ. of Edinburgh Wednesday, December 12, 12:00-1:30 PM Lunch Break Wednesday, December 12, 1:30-3:00 PM North Ballroom, Modeling and Performance Evaluation Chair: Makoto Amamiya, Kyushu University l: Performance Analysis of Hierarchically Structured Multiple Bus Multiprocessor System A.K. Ramani, N.R. Gore, Devi Ahilya Univ., A.K. Shah, and P.K. Chande, S.G.S. Inst. of Technology and Science l: A Comprehensive Modeling for Performance Evaluation of Regular Interconnection Network Calvin C.-Y. Chen and Hee Yong Houn, University of North Texas s: A Decomposition Approach for Analysis of Parallel Processing Systems Krishna M. Kavi, Srinivasan R. Kuthalam, and Akshay K. Deshpande, Univ. of Texas at Arlington s: Modeling the Execution of LOTOS Specifications by Cooperating Extended Finite State Machines Adriano Valenzano, R. Sisto, Politecnico di Torino, and L. Ciminiera, Universita di Bari s: Performance Measurement and Modeling on a Shared Memory Multiprocessor Through Message Passing Xiaodong Zhang and Pattabiram Srinivasan, Univ. of Texas at San antonio South Ballroom, Neural Networks Chair: Joydeep Ghosh, UT-Austin l: Modeling the Retinal Horizontal Cell Layer on a Massively Parallel Processor: A Detailed Neural Network Model Anthony L. Kimball and Raimond L. Winslow, Univ. of Minnesota l: A Probabilistic Inference Method with Multiple Evidences and its Implementation Using a Layered Network Akimichi Tanaka and Osamu Nakamura, Nippon Telegraph & Telephone Corp. s: ConSTrainer: A Generic Toolkit for Connectionist Dataset Selection Apostolos N. Refenes, University College London s: Multisensor Fusion Using Neural Networks Richard L. Holmberg and Joydeep Ghosh, University of Texas at Austin s: Ariel: A 100 Gigaflops Simulator for Connectionism Research Gary Frazier, Texas Instruments Wednesday, December 12, 3:00-3:30 PM Break Wednesday, December 12, 3:30-5:00 PM North Ballroom, Algorithms VI Chair: Alex Stoyenko, New Jersey Institute of Technology l: On Computational Limitations of Neural Network Architectures Achim G. Hoffmann, Technische Universitat Berlin l: On the Parallelization of Some Finite Difference Techniques Peter E. Raad and Abraham N. Varghese, Southern Methodist Univ. s: The Parallel Complexity of Queue Versus Stack Breadth First Search Raymond Greenlaw, Univ. of New Hampshire s: Mapping Precedence Trees to Hypercubes and Meshes Stuart Ullman and B. Narahari, George Washington Univ. s: Near-optimal Heuristics for Schedulings on Task-dependent Machines Kenneth C.K. Luo, Yuan-chieh Chow, and Richard Newman-Wolfe, Univ. of Florida South Ballroom, Networks III Chair: Dharma P. Agarwal, NC State University l: Simulating Parallel Neighboring Communications Among Square Meshes and Square Toruses Lixin Tao and Eva Ma, Concordia Univ. l: Compressing Cube-connected Cycles and Butterfly Networks R. Klasing, R. Luling, and B. Monien s: Performance Properties of NULL Message Based Distributed Simulation of Queuing Networks Devendra Kumar and Saad Harous, Case Western Reserve Univ. s: On Finding Maximal Subcubes in Residual Hypercubes M.A. Sridhar and C.S. Raghavendra, Univ. of South Carolina s: The Embedding Kernel on the IBM Victor Multiprocessor for Program Mapping and Network Reconfiguration Eva Ma and Dennis G. Shea, IBM Thomas J. Watson Research Center