robert%zeus@swanee.ee.uwa.oz.au (Roberto Togneri) (11/08/90)
Hi again, I've received plenty of replies on my problem with slow T800's. The common thread in all the answers was: - the T800 on-chip memory is not used by default and has to be specified by the user. - occam is better (!) I've since attempted to use the on-chip memory (3L C v2.1 allows placing the stack and code on the on-chip memory) and the 10 transputers now go 2.8 times faster than our IRISes as compared to the original 1.5 times. In case people are wondering we are using the Definicon TPAR transputer board (20 MHz) for the T800's. Our IRIS also has the following stats: IP4 Processor FPU: MIPS R2010A/R3010 VLSI Floating Point Chip Revision: 1.5 CPU: MIPS R2000A/R3000 Processor Chip Revision: 1.6 Data cache size: 32 Kbytes Instruction cache size: 64 Kbytes Main memory size: 8 Mbytes I'd like to thank all those people who replied. However in view of some of the comments I have some more queries: - Why is occam better than any parallel C compiler? Any benchmark tests on their relative performance to prove this? - Is there a parallel C compiler which is definitely better than 3L C v2.1 in terms of program execution speed? - Finally is there is any software to perform topologically independent routing of transputers (i.e. painless message between a transputesr node and any other node)? Hope somebody can help clarify some of these concerns. Thanks, -- Dr. Roberto Togneri Dept. of EE Engineering Phone: +61-9-380-2535 The University of Western Australia Fax: +61-9-380-1065 NEDLANDS WA 6009 Email: robert@swanee.ee.uwa.oz.au