clayton@multi.ee.usu.edu (Peter Clayton) (02/11/91)
TRANSPUTING '91 - Papers, Tutorials and Registration Details
TRANSPUTING '91
The World's Leading Conference on Multiprocessing
22 - 26 April 1991
Sunnyvale Hilton Inn, California
Transputers are the revolutionary microprocessors for multiprocessing which
have outsold all other 32-bit RISC architectures. They are fuelling explosive
growth in science and engineering by extending the ability to solve complex
problems fast, elegantly and at reasonable cost.
Highlights of TRANSPUTING '91 will include :
* A complete technical disclosure of the next generation INMOS H1 transputer,
which will offer 150 MIPS and 20 MFLOPS peak performance, as well as
enhanced support for multiprocessing and interprocessor communications.
* Five invited speakers from the U.S.A., the U.K. and Japan.
* 67 contributed papers, fully-refereed and selected to present a wide range
of parallel processing techniques, applications and experiences.
* A wide ranging tutorial program which will be invaluable as an
introduction to multiprocessing hardware and software techniques, to
show how transputer technology may be used to support specific
application areas, and how transputers can play an important part in
the teaching of concurrency and parallelism.
* The opportunity to meet experienced transputer users drawn from
every continent, to discuss how multiprocessing can simplify the design
of your applications and how to get started.
* Exhibitors sponsoring the conference include SGS-THOMSON Microelectronics,
ESPRIT, Parsytec Inc., Paracom, Parasoft, Transtech Parallel Systems,
JMI Software Consultants, Inc., Yarc Systems Corporation, Distributed
Software Ltd, 3L Ltd., A.T. Barrett & Associates, Computer Systems
Architects, Benson Computer Research Corporation, Division Limited,
Mechanical Intelligence, Archipel S.A., with others to be confirmed.
Non-commercial demonstrations of transputer applications will also be
present.
TRANSPUTING '91 builds upon the previous successful meetings of the
many Transputer and Occam User Groups worldwide, and is being organized
by representatives of these Groups - the World Transputer User Group
Committee.
The World's Leading Conference on Multiprocessing
=================================================
If you're investigating the use of parallel or multiprocessing in any
application, be sure not to miss TRANSPUTING '91. This international event
includes five days of selected presentations, tutorials and workshops on
the powerful concepts of parallel computing based upon communicating process
architectures, and will feature a full technical disclosure of the
next generation transputer, codenamed H1.
Invited speakers include representatives from Fujitsu Labs, Harvard
University, and IBM's T.J.Watson Research Centre. A concurrent exhibition
will support the conference themes of performance and scalability, porting
existing systems, parallelization paradigms, formal methods and security,
programming languages, support environments, standards, and applications.
Applications discussed and demonstrated at TRANSPUTING '91 will include
embedded real-time systems, workstations, supercomputers, laser printers,
disk arrays, image processing, global positioning by satellite, artificial
intelligence, databases, and the testing of scientific and mathematical
theories.
So... plan to find out what transputing is all about. See state-of-the-art
application demonstrations and product exhibitions from around the world.
Gain an in-depth understanding of the new software and hardware technologies
enabled by the transputer. Discover H1. Learn why transputers make sense -
today and for the future.
Endorsers of TRANSPUTING '91
============================
This conference is organised in cooperation with :
* The Institute of Electrical and Electronics Engineers (U.S.A.)
* ESPRIT (European Community)
* The Institute of Electronics, Information and Communication Engineers (Japan)
* The British Computer Society
* The Institute of Electrical Engineers (U.K.)
* The Institute of Physics (U.K.)
* Institut National de Recherche en Informatique et en Automatique (France)
* Centre National de la Recherche Scientifique (France)
* The Parallel Processing Connection (U.S.A.)
* The New Zealand Computer Society
* The Oregon Advanced Computing Institute (U.S.A.)
* The Edinburgh Parallel Computing Centre (U.K.)
* The SERC / DTI Transputer Initiative (U.K.)
* The Center for the Development of Advanced Computing (India)
and others
Special Invited Speakers
========================
Mr. Riichirou Take and Mr. Yasuo Noguchi
Researchers, Artificial Intelligence Laboratory, Fujitsu Laboratories Ltd.
"An architecture for parallel database computing"
The paper proposes an MIMD computer aimed at database processing and
general purpose applications. An experimental system has been made using
32 T800s as processing nodes and 32 for Dragon Net, a binary n-cube
structured network which can optimally process all-node-to-all-node
communication based on a simple rule.
Mr. Take and Mr. Noguchi are researching into concurrency control for
distributed database management systems, and parallel architecture and
algorithms for speeding up database operations. Mr. Take has a degree in
Mathematical Engineering and Information Physics from the University of
Tokyo. Mr. Noguchi has a Masters degree in Pharmaceutical Science from
the University of Tokyo.
Mr. Jonah McLeod
Editor, Electronics
"An industry-wide perspective on parallel and multi- processing"
Jonah McLeod has been with Electronics and Electronic Design since 1979,
writing on the whole spectrum of electronic equipment. Prior to this he
managed the Apple Computer and Intel Corp. accounts at Regis McKenna PR,
before which he was west coast editor of Computer Design. He has written
several books on computers, computer peripherals and CAD, and has a
Bachelor of Science degree from the University of Texas.
Dr. David May
Manager, Transputer Architecture and Development, INMOS
"Towards general purpose parallel computers"
David May is currently working at INMOS on the architecture of a new
product range for introduction in 1994. He graduated from Cambridge
University with a degree in Computer Science and has published about 45
papers and 15 patents. He is Visiting Professor of Engineering Design at
Oxford University and has an honorary DSc from Southampton University for
his contributions to the development of parallel computing.
Professor Leslie Valiant
Harvard University
"Bulk-synchrony: a bridging model for parallel computation"
The success of the Von Neumann model of sequential computation is
attributed to the fact that it is an efficient bridge between software and
hardware. This paper argues that an analogous bridge between software and
hardware is required for parallel computation if it is to become more
widely used, introduces the bulk-synchronous parallel model as a candidate
for this role, and supports the suggestion by giving a number of results
that quantify its efficiency.
Professor Valiant is currently Gordon McKay Professor of Computer Science
and Applied Mathematics at Harvard University. His current research
interests are computational complexity, machine learning, and the theory
of parallel algorithms and architectures. In 1986 he received the
Navanlinna prize for theory of information processing from the
International Mathematical Union.
Mr. Dennis G. Shea
Modular Microsystems Group Manager, IBM T.J.Watson Research Center
"IBM Victor V256"
Victor is a family of partitionable transputer-based multiprocessors that
have been designed at IBM Research to provide researchers with a platform
for experimentation in the area of highly parallel message passing MIMD
machines with distributed memory. Applications running on Victor cover a
variety of scientific and engineering topics such as VLSI waveform
relaxation based circuit simulation and Quantum Monte Carlo simulations
for exploration of high temperature superconductors.
Dennis Shea's research focuses on the design and development of high
performance distributed memory parallel processors and their use in
solving real applications. He is a Ph.D. candidate in the Department of
Computer and Information Science at the University of Pennsylvania, and
has a Master's degree in Computer Systems from Florida Atlantic
University.
H1 TRANSPUTER DISCLOSURE
Ian Pearson, Director of Technology, INMOS
Wednesday afternoon's session will feature a complete technical disclosure
of INMOS' next generation transputer, codenamed H1.
The key features of H1 are a high performance pipelined superscalar
processor and major support for multiprocessing applications. Peak
performance will be more than 150 MIPS and 20 MFLOPS. INMOS, a member of
the SGS-THOMSON Microelectronics group, is the recognized leader in
parallel and multi- processing, and H1 represents a major advancement in
parallel computing and high speed communications.
The transputer architecture is unique in providing hardware support for
process scheduling and specific instructions for interprocess
communication. As the computational loads on embedded processors
increase, the ability to produce scalable multiprocessor systems is
crucial. H1 represents a significant advance in the transputer's already
proven capabilities in parallel and multiprocessing.
The design goals for H1 were to enhance the transputer's position as the
premier multiprocessing microprocessor, and to establish a new standard in
single processor performance, while maintaining compatibility with
existing transputer products. This session will disclose the means by
which these have been achieved, and time has been scheduled for Mr.
Pearson to field questions from the audience.
Contributed Papers
==================
67 papers have been selected by referees from all over the world. The
choice of papers was based upon their technical quality, the relevance and
originality of the applications described, and their suitability for
presentation at this meeting. A wide range of industrial and academic
organizations will be represented. The papers will be scheduled as either
two or three parallel themed sessions. The papers will be published by
IOS Press (Amsterdam) in the series which already contains all the
proceedings from the other Transputer and Occam User Group meetings
previously held. A copy of the proceedings will be given to each delegate
upon registration.
Tutorials
=========
The tutorials listed in the timetable below are being provided by
experienced members of the transputer community as an inexpensive
educational service for delegates to TRANSPUTING '91. All will attempt to
provide a practical guide to the topics presented, so that attendees may
rapidly apply the knowledge gained.
Call for Posters
================
Space will be available for a limited number of posters on each of the
three days of the conference. Authors are invited to submit one-page
abstracts on subjects of a timely nature or on techniques which are
better presented in a written form. These abstracts may be submitted
at any time to the addresses below; the committee will attempt to
signal acceptance within a few days. The final posters should fit onto
a maximum of three display boards, each of size 32" high by 21" wide.
To underline the educational aspects of the conference, authors are
also invited to bring small posters (maximum size 20" by 13") detailing
individual student projects using transputer technology. These
posters will be displayed during the conference and tutorial
sessions, in available spaces, and will not be refereed.
Abstracts should be submitted to :
Prof. P.H. Welch, Dr. G.S. Stiles,
Computing Laboratory, Dept. of Electrical Engineering,
The University, Utah State University,
Canterbury, Logan,
Kent CT2 7NF UT 843222-4120
U.K. U.S.A.
Phone : +44 227 764000 Phone : +1 801 750 2806
Fax : +44 227 762811 Fax : +1 801 750 3054
Email : phw@ukc.ac.uk Email : stiles@cc.usu.edu
WOTUG Organising Committee
==========================
Professor Peter H. Welch (Chair, OUG), University of Kent, U.K.
Dr. G.S. Stiles (Chair, NATUG), Utah State University, U.S.A.
Professor T.L. Kunii (Chair, OUG-Japan), University of Tokyo, Japan
Dr. K.S. Venkatesh, Center for the Development of Advanced Computing,
Bangalore, India
Dr. John Hulskamp (Chair, AOTUG), Royal Melbourne Institute of Technology,
Australia
Dr. Ian Graham (Secretary, NZ-TUG), University of Waikato, N.Z.
Professeur Traian Muntean, IMAG-LGI Laboratory, Grenoble, France
Joachim Stender (Chair, DOIT), Brainware GmbH, Berlin, F.R.G.
Dr. Raphael Lins (Chair, OUG-LA), University of Recife, Brazil
Ir. Andy Bakkers, Twente University, Netherlands
Dr. John Board, Duke University, U.S.A.
Ron S. Cok, Eastman Kodak Company, Rochester, NY, U.S.A.
David Fielding, Cornell Theory Center, U.S.A.
Mitchell Loebel, Parallel Processing Connection, U.S.A.
Dr. Alan Wagner, University of British Columbia, Canada
Dr. Gordon Harp, Royal Signals and Radar Establishment, U.K.
Professor A.J. Hey, University of Southampton, U.K.
Dr. Geraint Jones, Programming Research Group, Oxford University, U.K.
Dr. Jon Kerridge, National Transputer Support Centre, Sheffield University, U.K.
Roger Peel, University of Surrey, U.K.
Colin Upstill, Roke Manor Research, U.K.
Hugh Webber, Royal Signals and Radar Establishment, U.K.
Dr. John Wexler, Edinburgh Parallel Computing Centre, U.K.
Mark Hopkins (Secretary, NATUG), SGS-THOMSON Microelectronics, Colorado
Springs, U.S.A.
Kazuto Matsui (Secretary, OUG-Japan), SGS-THOMSON Microelectronics, Tokyo, Japan
Dr. Michael Poole (Secretary, OUG), INMOS, Bristol, U.K.
Brian Raines, Executive Meeting Management, U.S.A.
Conference Programme
====================
Monday, 22nd April 1991
-----------------------
Tutorials on the fundamental principles underlying transputer technologies
and various design paradigms for exploiting them. These tutorials are of
half-day duration unless indicated below.
08:30 - 12:30 Morning tutorial session
Communicating Process Architectures and Transputer Overview
Formal Methods for Transputing
Logic Programming on the Transputer
Transputer Programming Environments (first half)
12:30 - 14:00 Lunch
14:00 - 18:00 Afternoon tutorial session
Designing Parallel - Going Sequential
Parallelizing Existing Code
Mixed Language Programming on the Transputer
Transputer Programming Environments (second half)
Tuesday, 23rd April 1991
------------------------
08:00 - 09:00 Registration
09:00 - 10:00 Opening and invited speaker - Dennis Shea (IBM)
10:00 - 10:30 coffee
10:30 - 12:30 Papers in two parallel streams :
Image Processing
----------------
Applications of a Parallel Image Processor
R.S. Cok, Eastman Kodak Company, U.S.A
A Transputer Based Image Processing System for Vehicle Guidance
U. Franke & S. Mehring, Daimler Benz AG, Germany
A Large Area, High Resolution Image Analyser For Polymer Research
A.R. Clarke, N. Davidson & G. Archenhold, Leeds University, U.K.
Parallel 3D Vision for Vehicle Navigation and Control
M. Rygol et al, University of Sheffield, U.K.
Routing, etc.
-------------
Parallel Routing Algorithms for Kilonode
F.H. Schlereth et al, Syracuse University, U.S.A.
A Monitoring System for a Transputer-Based Multiprocessor
M. Aspnas & T. Langbacka, Abo Akademi, Finland
The Implementation and Use of H1-Compatible Virtual Channel Software on
All Types of Transputers
Kirk Bailey, Logical Systems, U.S.A.
FFDE: Simulation of MIMD Architectures on Transputers
P. Grabienski, K.D. Gundermann & R. Simansky, University of Dortmund,
West Germany
12:30 - 14:00 Lunch
14:00 - 15:30 Papers in three parallel streams :
Mappings, etc
-------------
Transparent Problem Decomposition and Mapping - a CS Tools Based Implementation
T. Tollenaere & G.A. Orban, Katholieke Universiteit Leuven, Belgium
Performance of SUN-Transputer Interfaces : some surprises
M.S. Atkins, Simon Fraser University, Canada
Occam Implementation of Process-to-Processor Mapping on the Hathi-2 Transputer
System
H. Shen, Abo Akademi, Finland
Numerical
---------
A Transputer-Based Parallel Implementation of a Median Filtering Algorithm
M. Avvenuti, G. Corsini & C.A. Prete, Universita di Pisa, Italy
Parallel Overrelaxation Algorithms for Systems of Linear Equations
R.D. da Cunha & T. Hopkins, University of Kent at Canterbury, U.K.
The Impact of New Parallel Architecture on High Performance Applications
F. Wray, Parsytec GmbH, West Germany
Technical & Industrial Applications
-----------------------------------
Adaptive Optics
Peter Wizinowich, M. Lloyd-Hart & R. Angel, University of Arizona, U.S.A.
Development of the CAD/CAM System based on Parallel Processing and the Inverse
Offset Method
H. Suzuki et al, Kyusyu Institute of Technology, Japan
Transputers for Real-time Electronic Warfare Support Measures (ESM) Signal
Processing
A.M. Feltham, S. Cussons & J. Roe, Admiralty Research Establishment, U.K.
15:30 - 16:00 tea
16:00 - 18:00 Papers in three parallel streams :
Tools & Operating Systems
-------------------------
TIPS - Transputer-based Interactive Parallelising System
A. Wagner et al, University of British Columbia, Canada
TOOS : A Transputer-Oriented Operating System
B. Roelofs, Yarc Systems Corporation, U.S.A.
Linda Sub System on Transputers
K.H. Shekhar & Y.N. Srikant, Indian Institute of Science, India
Distributed Operating System for H1 Transputer Networks
C. Tricot, M. Guillemont & H. Yassale, Archipel S.A., France
Mappings
--------
A Multiprocessor Testbed for Generalised Systolic Computation
Stephen B. Seidman, Auburn University, U.S.A.
Parallelisation of the Fast Multipole Method using the B012 Transputer Network
James F. Leathrum, Jr. & J.A. Board, Jr., Duke University, U.S.A.
MARC: A Tool for Automatic Configuration of Parallel Programs
J.E. Boillat, N. Iselin & P.G. Kropf, University of Berne, Switzerland
Post-Game Analysis on Transputers
J.P.E. Sunter, E.C. Koenders & A.W.P. Bakkers, University of Twente, Netherlands
Technical & Industrial Applications
-----------------------------------
Benson Transputer Products
J.W. Benson, Benson Computer Research Corporation, U.S.A.
The Battlefield Sensor Simulator
A.D. Higham, G.P. Williamson & J.R. Hunt, Roke Manor Research Limited, U.K.
Processing of Offset Vertical Seismic Profiling Data using Transputers
G. Duncan & L. Leung, BHP Central Research Laboratories, Australia
Transputer Hardware Applications and Real-Time Data Acquisition
R. Taylor & S. Taylor, Douglas Engineering, U.S.A.
Wednesday, 24th April 1991
--------------------------
08:00 - 10:00 Papers in two parallel streams :
Language Issues
---------------
Extended Occam for Library Design
L.M. Delves, G. Howard & D. Wilkinson, University of Liverpool, U.K.
Formal Support for Distributed Systems: Occam and the Transputer
G. Barrett & B. Sufrin, INMOS Limited, U.K.
A Parallel X-Windows Server (A Case Study on Occam and Programming-in-the-Large)
C.J. Willcock & P.H. Welch, University of Kent at Canterbury, U.K.
Extending C++ with Communicating Sequential Processes
J.M. Adamo, Ecole Normale Superieure de Lyon, France
Fault Tolerance
---------------
Adding Hardware and Software Fault Tolerance to a Transputer-Based Parallel
Database Machine
R.J. Oates, University of Sheffield, U.K.
Transputers and Fault Tolerance
N. Brock, Draper Laboratory, U.S.A.
A Fault Tolerant Transputer System For Numerical Weather Prediction
I. Graham, Y.Q. Tian & D. Purnell, University of Waikato, New Zealand
High Availability Transputing Systems
R. Beton, J. Kingdon & C. Upstill, Roke Manor Research, U.K.
10:00 - 10:30 coffee
10:30 - 11:30 Invited Speakers - Riichirou Take & Yasuo Noguchi (Fujitsu)
11:30 - 12:30 Invited Speaker - Les Valliant (Harvard)
12:30 - 14:00 Lunch
14:00 - 18:00 INMOS H1 technical disclosure
Evening Conference dinner
Invited Speaker - Jonah McLeod (Electronics)
Thursday, 25th April 1991
=========================
08:00 - 10:00 Papers in two parallel sessions
Hardware
--------
Transputer and Local Area Networks - A Model for Integration
L. Manasiev, Bulgarian Academy of Sciences, Bulgaria
The Mad-Postman Network Chip
C.R. Jesshope, University of Surrey, U.K.
Mousetrap : a Miniaturised Supernode for Terrain Modelling
K.J. Palmer & H.C. Webber, Royal Signals & Radar Establishment, U.K.
The DataMesh Research Project
J. Wilkes, HP Laboratories, U.S.A.
Prolog, AI, etc.
----------------
Implementation of RAPID on a Multi-Transputer Architecture
J. Walter, University of Stuttgart, Germany
A Hybrid Transputer Based Architecture for Parallel Logic Language Execution
J.P. Gray & I.E. Jelly, Sheffield City Polytechnic, U.K.
Parallel Interpretation of Prolog on Transputer Networks
M. Avvenuti, P. Corsini & G. Frosini, Universita di Pisa, Italy
Genetic Packing of Rectangles on Transputers
B. Kroger, P. Schwenderling & O. Vornberger, University of Osnabruck, Germany
10:00 - 10:30 coffee
10:30 - 11:30 Invited Speaker - David May (INMOS)
11:30 - 12:30 Panel Discussion
12:30 - 14:00 Lunch
14:00 - 15:30 Papers in three parallel sessions
Formal Methods, Image Processing
--------------------------------
A Formally Specified Decentralised Architecture for Multi-Sensor Data Fusion
J. Manyika, S. Grime & H.F. Durrant-Whyte, University of Oxford, U.K.
Formal Methods in the Design of the H1 Transputer
A.W. Roscoe, Formal Systems (Europe) Limited, U.K.
Transputer Implementation of a Perspective View Generator
W. Baer Nascent Systems Development Inc, U.S.A.
Neural Networks
---------------
A Transputer-based Implementation of Holographic Neural Technology
J. Sutherland, AND Corporation, Canada
Coherent Oscillation in Neural Networks : Its Transputer Simulation
T. Bossomaier, The Australian National University, Australia
Optimisation of Network Structure using Genetic Techniques implemented on
Multiple Transputers
N. Dodd, D. Macfarlane & C. Marland, Royal Signals & Radar Establishment, U.K.
Real Time / Robotics
--------------------
The Suitability of Transputers for Use in an Autonomous Free-Flying Robot
K.A. Grimm, NASA-JSC, U.S.A.
Transparent Distributed Real-Time processing with TRANS-RTXc and Transputers
E. Verhulst & H. Thielemans, Intelligent Systems International NV/SA, Belgium
Design Analysis of a Priority Driven Scheduler for Transputers
A. Bakkers et al., University of Twente, Netherlands
15:30 - 16:00 tea
16:00 - 18:00 Papers in three parallel sessions
Performance / Routing
---------------------
Communication, Computation and Busyness in A Transputer-Based Parallel System
T. Hintz & X. Ma, University of Technology, Sydney, Australia
The Hydra Parallel Worm
D.J. Johnston Rutherford Appleton Laboratory, U.K.
Towards a Hybrid Message Passing Regime for Very Large Multi-Processor Machines
P. Jones & H. Cha, University of Manchester, U.K.
Using a Transputer Network to Solve Branch-and-Bound problems
G.P. McKeown et al., University of East Anglia, U.K.
Image Processing
----------------
Developing the MGI Workstation - A Multi-Transputer Based Medical Graphics
System
A.C. Tan & R. Richards, University College, London, U.K.
Visual Software Agent Built on Transputer Network with Visual Interface
W. Wongwarawipat et al., University of Tokyo, Japan
A Versatile Parallel Computer Architecture for Machine Vision
E. Hirsch et al., Universite Louis Pasteur, France
Still Picture Coding using Transputer and DSP
H. Mizusawa & S. Kato, Nippon Steel Corporation, Japan
Real Time
---------
The Implementation of a Transputer-Based Rudder Roll Stabilization system
(RRS) for ships using a CASE tool
K.C.J. Wijbrans & A.W.P. Bakkers, Van Rietschoten & Houwens, Netherlands
A High Performance Transputer Based Controller for Power Electronic Motion
Control Application
D.C. Levy et al., University of Natal, South Africa
Performance Evaluation Tools for Real-Time Control and Simulation
F.G. Nocetti & P. Fleming, University of Wales, Bangor, Wales
Real-Time Control of a Sorting Conveyor
C. Davidson, Mechanical Intelligence, U.S.A.
The Use of Transputers for Real-Time Traffic Measurement on MAGNET II
A.A. Lazar, G. Pacifici & J.S. White, Columbia University, U.S.A.
Evening Awards dinner
Friday April 26, 1991
---------------------
Full-day workshops on transputer applications and advanced techniques
08:30 - 12:30 Morning tutorial session
12:30 - 14:00 Lunch
14:00 - 18:00 Afternoon tutorial session
Embedded Real-time Control Systems
Real-time Kernels for C Programmers
Designing Parallel - a hands-on workshop
Image Processing - a hands-on workshop
Scientific Computing
Office Automation Applications
Communications Applications
Artificial Intelligence
The Helios Operating System - a hands-on workshop
The TRANSPUTING '91 tutorials
=============================
These tutorials are being provided by experienced members of the
transputer community as an inexpensive educational service for delegates
to TRANSPUTING '91. All will attempt to provide a practical guide to the
topics presented, so that attendees may rapidly apply the knowledge
gained. The initial six tutorials in this description are of half-day
duration, and the remainder are a full day in length. See the conference
programme for details of their scheduling. The conference committee
reserves the right to cancel tutorials which are insufficiently
subscribed.
Communicating Process Architectures and Transputer Overview
===========================================================
This tutorial will serve as an introduction to parallel processing using
communicating processes.
Distributed memory multiprocessing is becoming acknowledged as the
most promising parallel processing technique for a large range of
applications, due to its scalability - as extra processors are added
to a configuration, they bring their own memory which may be accessed
independently of the rest. The INMOS transputer comprises a
high-performance RISC-like processor, on-chip memory, specialised
communication engines and an instruction architecture designed to
support inter-transputer communication. Over the past several years,
users of the transputer have developed theoretical and practical
models of this form of communication, as well as the tools
necessary to harness the parallelism which may be achieved.
This tutorial is designed to prepare delegates for the material to be
presented throughout the week. The software element will concentrate on
the principles of communication, synchronisation, load balancing and
deadlock. The hardware element will highlight the important features of
the transputer architecture and show how easily current transputer
products may be incorporated in a range of hardware designs.
Formal Methods for Transputing
==============================
Formal Systems (Europe) Limited
Intended audience: Engineers with prior exposure to Transputers and occam.
Objectives: To give an overview of the benefits of formal methods and a
limited repertory appropriate for use in parallel programming.
Introduction : What are formal methods, and how can they help?
Why formal methods are particularly necessary for
concurrent programming.
Why occam is particularly well suited to formal analysis:
clean semantics and theoretical underpinning.
The Laws of occam Programming.
Transformation of occam programs.
Simple ways of avoiding deadlock.
Case studies:
a small worked example;
how the T800 FPU verification worked.
Pointers to further sources of information and tuition.
Logic Programming on Transputers
================================
P. Kacsuk (Queen Mary & Westfield College, London, U.K.)
M. Wise (University of Sydney, Australia)
Recently, significant efforts have been made to implement logic
programming languages on distributed memory systems and particularly on
multi-transputers. This tutorial is intended to present the main
directions in the progress of logic programming languages towards their
efficient implementation on distributed memory systems. It surveys the
major problems of implementing logic programs on multi- transputer systems
and summarizes the solutions provided by the existing commercial systems
and undergoing research projects.
Distributed logic programming systems can partitioned into three main
classes:
(1) Standard Prolog systems
(2) Committed choice Prolog systems
(3) Distributed Prolog Systems
On the language side, Standard Prolog systems introduce at most small
modifications to Prolog. However on the implementation side they require
new execution models and a number of new implementation techniques to
achieve a speedup proportional with the number of applied processing
elements.
Committed choice logic languages have been designed to exploit as much
parallelism as possible on parallel computers. Development of these
languages is strongly influenced by the demand of efficiently implementing
them on parallel computers. The tutorial surveys the major steps of the
progress of these languages related with their implementation techniques
on distributed memory machines.
The first two classes of distributed logic programming systems require the
realization of fine-grain parallelism and therefore a large number of
messages. Distributed Prolog languages were proposed for exploiting
coarse-grain parallelism and therefore they provide explicit user defined
task generation facilities. Though the implementation techniques of these
languages inherit much from the other two classes, they require some new
approaches particularly in implementing distributed backtracking.
Attendees are expected to be familiar with sequential Prolog.
Designing Parallel - Going Sequential
=====================================
P.H. Welch (University of Kent, U.K.),
R.M.A. Peel (University of Surrey, U.K.)
This tutorial will illustrate a selection of program specification, design
and implementation techniques suitable for use with the transputer.
Problem decomposition will be discussed in the context of a Communicating
Sequential Processes (CSP) model, and methods of avoiding deadlock,
maximising performance and reusing common program modules will be
presented.
Parallel programming structures to support one's algorithms will form
the major part of this tutorial. These include :
* Each parallel process can restrict access of its data objects by the
other processes, and can thus be seen to have useful object-oriented
qualities. Following the overall system design, these parallel processes
may be written, simulated and tested independently of each other, right up
to final integration.
* Termination of parallel processes is central to the CSP architecture.
Methods for terminating groups of parallel processes of arbitrary
complexity will be discussed.
* When writing high-performance parallel applications which communicate
large volumes of data, buffering is necessary. Various configurations of
double buffering, pipelines, multiplexers and demultiplexers will be shown
to maximise throughput with varying degrees of complication. The
important use of overwriting buffers in real time systems will also be
studied.
* The advantages of parallelism and communication to replace the use
of interrupts, signals and polling will be demonstrated.
Having illustrated the benefits and simplicity of designing software as
collections of parallel processes, the tutorial will conclude by
highlighting recent work on serialising parallel processes. This will
show how parallel design methods can be used to improve the design of
sequential code to accommodate the lack of parallelism in the underlying
execution hardware.
Mixed Language Programming
==========================
A. Debling (INMOS Limited)
J. Kerridge (University of Sheffield, U.K.)
The aim of this half-day tutorial is to show how languages such as C,
FORTRAN and Pascal can be used effectively in transputer-based systems.
This reflects the fact that there are a large number of existing programs
which could be utilised in such systems.
The tutorial will emphasise not only the role of these traditional
sequential languages but also the role of occam to implement the parallel
parts of a system design. By means of examples it will be shown how
functions, subroutines and procedures written in these other languages can
be easily incorporated into an occam harness, thereby ensuring that the
parallel aspects of the system are implemented using the most appropriate
language and the sequential parts also use the most suitable language or
existing code.
Mechanisms will also be discussed that preserve the syntax and semantic
checking provided by occam channel protocols when these channels are
connected to processes not written in occam. This is of vital importance
if the security of occam channel communication is to be retained within
the parallel part of a mixed system.
The tutorial will use a number of programmed examples to expound the
techniques that a programmer will need to assimilate. These examples will
be taken from current projects and systems which are being developed for
different application environments.
The concept of generally available harnesses for running an existing
sequential program will also be discussed. Such harnesses enable the
performance of a single transputer implementation of an existing system to
be quickly evaluated. For suitable applications, these harnesses also
provide a means of parallelising the system with very little effort. The
characteristics of suitable applications will be discussed.
Parallelising Existing Code
===========================
J. Wexler and colleagues from the Edinburgh Parallel Computing Centre
"Will it run our existing applications faster?" - for many users, this is
the crucial question in deciding whether to include Transputers among
their computing resources. If the answer is important to you, then you
should attend this tutorial. Whether you are completely new to Transputers
(perhaps even to parallel computing), or knowledgeable, experienced and
confident about developing new parallel applications, you do not need to
be told what magic the Transputer can perform in general, but whether, and
how, that magic can be worked on your existing code.
That will be the emphasis in this half-day of presentations by experts in
parallelisation, designed to set out the possibilities and approaches that
are tried and tested in practice, so that you can decide how they can be
applied to your own software. Sessions will cover
- Introduction and overview
- Effective paradigms
- Hazards, problems and performance issues
- Support tools, and automating the parallelisation process
- Pre-packaged schemes
- A representative software environment
The tutorial is aimed at software managers, software engineers and
programmers. It will concentrate on parallelising software written in
Fortran and C. It assumes no special background knowledge.
The tutorial is coordinated by the Edinburgh Parallel Computing Centre, of
the University of Edinburgh (Scotland), which is one of Europe's major
centres of parallel computing. EPCC is involved in partnerships and
affiliations with major international companies, and has extensive
experience of parallelising commercially important applications.
Transputer Programming Environments
===================================
G.S. Stiles (Utah State University, U.S.A.),
P.G. Clayton (Rhodes University, S.A.)
with contributors from various vendors
This tutorial will be devoted to the latest program development
environments for parallel systems.
Those using transputers and other parallel processors realize that
developing programs to run on such systems is often a tedious and
time-consuming chore. The task of explicitly managing the routing of
messages is particularly difficult. The problem is greatly magnified when
the user must adapt to changing topologies or to completely different
machines. Debugging a program running on multiple processors can be a
nightmare. Commercial solutions to these problems, however, have begun to
appear.
Representatives of several firms have been invited to present technical
discussions of their products at this full-day session. These talks will
cover the latest offerings in program development tools for transputers
and similar systems. Emphasis will be placed on topology-independent and
machine-independent programming, dynamic debugging of multi-node programs,
and real-time environments. Several of the packages under discussion run
on parallel processors other than transputers, and on workstations.
Firms and products will include:
Cornell/Ohio State University: Trollius
Transtech: Genesys
Meiko: CS Tools
Strand: Strand
Parasoft: Express
MIMD Systems: Helios
JMI Software Consultants: Real Time Systems
Intelligent Systems Intl: TRANS-RTXc
Computer System Architects: Modula II and C tools
This tutorial will provide an excellent opportunity for old and new users
to become acquainted with the latest tools for developing parallel
programs.
Embedded Real-Time Control Systems
==================================
A.W.P. Bakkers (Twente University, Netherlands),
D. Koditschek (Yale University, U.S.A)
This tutorial / workshop will concentrate on the practical aspects of
developing transputer-based real-time systems. Most of the examples will
be drawn from two demonstrations and experiments.
Experiments in Robot Juggling : Transputer Based Real-Time Motion Control
-------------------------------------------------------------------------
A. Rizzi, L. L. Whitcomb & D. E. Koditschek ( Yale University, U.S.A.)
In a continuing program of research in robotic control of intermittent
dynamical tasks, we have constructed a three degree of freedom robot
capable of "juggling" a ball falling freely in the earth's
gravitational field.
The system consists of four major sections, all of which have been
implemented on a network of twelve transputers:
* A transputer based real-time stereo vision system capable of reporting
the position of a ball in space at 60 Hertz
* A juggling algorithm which continuously maps ball position and velocity
(as determined by a linear state observer) to an achievable robot
reference trajectory
* A distributed robot control architecture capable of performing low
level robot control at a rate of 1Khz
* Adaptive model-based robot control. Improved robot tracking
performance through use of smart controllers which "learn" the robot's
dynamics
* A new 3DOF direct drive robot based on variable reluctance motors
supplied by the Superior Electric Corporation.
The system senses ball position via the stereo vision system, and using
3-D triangulation produces an x-y-z position for the ball at 60Hz. The
x-y-z position of the ball is then passed into a linear observer, which
estimates current ball position and velocity at a rate much higher than
the output of the vision system. The resulting position and velocity
estimates are then processed at a rate of 1KHz by the juggling algorithm
to produce commands (robot position and velocity) to the robot
controller. Any of a family of robot control algorithms is then used to
produce torque commands for the robot.
The tutorial will work through the design, showing how transputers are
utilised in each section.
Transputer-Controlled Stepper Motor
-----------------------------------
The aim of this part of the workshop is to demonstrate by means of a
hands-on experiment, how parallelism provides both a unified design method
for a real-time control problem and a way of increasing system performance
as well.
The goal is to let the attendees design and implement a program that
controls a stepper motor using parallel design methods. The stepper motor
consists of eight coils and a rotating magnet. Each coil can be actuated
separately. Also, multiple coils can be actuated in order to obtain
intermediate positions of the rotor. Two user-defined function keys can
be programmed to control the motor movements, e.g. single step forward and
backward, or acceleration and deceleration of a continuous motion.
Several design and implementation methods will be given, to demonstrate
that parallel programming is simplicity itself, and can even be great fun!
The theme of this session will be "Thinking in Parallel".
Operating Systems and Real-time Kernels
=======================================
Julian Wilson, INMOS Strategic Applications Manager, will organise this
session on operating systems and real-time kernels.
The tutorial will cover :
* Transputer hardware support for real-time kernels
* Enhancements to the H1 family for kernels
* Industry-standard real-time kernels for the transputer - VRTX and C-Executive
* Transputer UNIX operating system strategy - HELIOS and CHORUS
Designing Parallel - a hands-on design workshop
===============================================
J. Kerridge (University of Sheffield, U.K.),
R.M.A. Peel (University of Surrey, U.K.)
This workshop will concentrate on the design issues of embedded systems.
The hands-on session will give delegates the opportunity, under
supervision, to design and implement a small parallel simulation program
which runs on a T222 transputer. This workshop has been prototyped at the
National Transputer Support Centre, Sheffield, in July 1990, under the
auspices of the Occam User Group Education and Training SIG.
The majority of the workshop will hinge around the design of a control
processor for a photocopier. This will eventually be animated on a T222
transputer training board, equipped with a range of peripheral interfaces
capable of emulating the buttons and displays of a photocopier.
Several different approaches to the design of the controller will be
presented, incorporating varying degrees of parallelism. The effects of
this parallelism on the device drivers, the central control logic and the
error recovery mechanisms will be examined, and the lessons learned may
explain some of the more irritating features of current commercial
products! The contrast between top-down and bottom-up design techniques
in parallel programming will also become apparent.
Following on from the design, there will be opportunities for the
delegates to program parts of the design, which can be fitted into the
alternative structural frameworks provided. This will provide valuable
experience of the protocols required between communicating processes,
and the security obtainable from compile-time checking of these
interfaces.
Apart from the practical aspects which are relevant to all transputer
users, the intention of this workshop is also to provide the opportunity
for educators (both industrial and academic) to come together and design a
real-time control application, and then to review the results and how such
programming experiences could be passed on to students. To further this,
the workshop will include a period when course design is discussed, and
when some of the educational posters (see elsewhere on this flyer) will be
examined.
Image Processing - a hands-on workshop
======================================
H.C. Webber (Royal Signals & Radar Establishment, U.K.),
S.R. Ruocco (Middlesex Polytechnic, U.K.),
D. Crookes (University of Belfast, U.K.)
Run previously under the auspices of the U.K. SERC / DTI Transputer
Initiative Image Processing Transputer Application Community Club
(IPTACC), this tutorial aims to cover the basic concepts of image
processing and then to relate these to using transputers to implement
them.
The tutorial will be of interest to those people who are considering the
potential of Image Processing and wish to understand how a transputer
implementation is different from a non-parallel implementation.
The morning tutorial lectures will be given by respected members of the
image processing and transputer communities, and will be accompanied by a
workbook containing the viewfoils used throughout the session. The topics
to be covered are:
* Introduction to Image Processing
* Image display using Transputers
* Image Processing using Transputers
The afternoon hands-on session is designed to give some experience of the
topics covered earlier in the day. Depending on the number of attendees,
the afternoon session may be organised as a series of demonstrations
instead. To obtain maximum benefit, attendees should be familiar with
occam and / or C.
Scientific Computing
====================
J. Wexler (Edinburgh Parallel Computing Centre, U.K),
H. Heller and K. Schulten, (University of Illinois, U.S.A),
T. Tollenaere (University of Leuven, Belgium),
N. Carmichael (Shell U.K.)
This tutorial presents a range of different parallel processing techniques
and application areas in many fields of science, including both basic
research and industrial applications. It demonstrates how the Transputer
can provide cost-effective solutions to previously intractable problems,
and how it opens up new possibilities for research and exploitation.
The tutorial is coordinated by the Edinburgh Parallel Computing Centre, of
the University of Edinburgh (Scotland), which is one of Europe's major
centres of parallel computing. The Centre runs several major parallel
computing systems, including one of the world's largest Transputer-based
multi-user services. This service is host to a large international
community of researchers, and the vehicle for an extensive range of
scientific applications.
Topics to be covered during the day include
- Neural networks
- A large molecular dynamics simulation using a systolic ring of transputers
- Scientific applications in the oil industry
- Computational fluid dynamics
- Finite element methods
- Cellular automata
and more besides.
The day will be divided into sessions of approximately one hour, each of which
will :
Survey the field of scientific applications in some specific area or
using some particular approach
or
Present significant results achieved using Transputers
or
Describe some interesting approach which may give you new ideas
for research and applications
Office Automation Applications
==============================
Stephen Maudsley, INMOS Strategic Applications Manager, will be organising
this session. It will involve presentations, workshops and demonstrations
of office automation products using transputers, including the upgrade
path to exploit H1 technology. The products will include :
* Laser printers - low-end raster image processors (RIPs) to high-end
Postscript interpreters.
* Disk arrays - exploiting the transputer and INMOS link technology for
multiple disk systems
* X-terminals - porting the X-server onto transputers
Communications Applications
===========================
Neil Richards, INMOS Telecoms Segment Manager, will discuss the use of
transputers in general purpose telecommunication systems, ranging from
LANs to public switching systems. The tutorial will include
presentations, workshops and demonstrations on the following topics :
* INMOS link technology for communications systems
* Using the transputer and INMOS link technology in LAN interfacing -
Ethernet, FDDI, token ring
* Using the transputer in next generation PABX and central office
switching systems - ISDN, ATM / STM
Artificial Intelligence
=======================
J. Stender & E. Hillebrand (Brainware GmbH, Germany),
S. Forrest (University of New Mexico, U.S.A.),
D. Macfarlane & I. East (University of Buckingham, U.K.)
The morning session of the workshop will provide an introduction and
overview of parallel genetic algorithms, and it will discuss fine-grained
parallel genetic algorithms. The session will be divided into three
roughly equal parts:
1. Introduction and overview of (sequential) genetic algorithms
- introduction (biology or computer science?)
- mechanical details of the algorithm
- why genetic algorithms work
- example applications
2. Theory of parallel genetic algorithms
- implicit parallelism
- explicit parallelism of population subdivision
- interactions among subpopulations
- explicit fine-grained parallelism
3. Fine-grained parallel genetic algorithms
- one processor per individual model
- replication strategies (conventional, location-based, resource-based,
pattern-based)
- implementation issues
- research questions
- example applications
The afternoon session of the workshop will focus primarily on the practical
aspects of implementing genetic algorithms on transputer networks. Many of
the issues raised, such as scalability, load balancing, efficiency and
deadlock freedom, have more general application in parallel processing.
The session will be divided into four parts of approximately equal length.
- General issues in scalable efficient implementations of fine-grained
parallel genetic algorithms on coarse grained transputer networks.
- Three parallel genetic algorithms, farming, migration and diffusion,
and their implementation on transputer networks.
- Applications and studies of parallel genetic algorithms. Evaluation
and comparison of the different models and implementations.
- Demonstration of implementations and visualisation software.
Question time.
The workshop will draw on work done in Europe using transputers and
parallel genetic algorithms and in particular the ongoing research at
Buckingham Univerity in the UK and GMD in Germany. Two major applications
of parallel genetic algorithms will be described, the solution of TSP
problems and the search for application specific structured neural
networks.
Attention will also be drawn to the practicality and cost effectiveness of
transputer networks used in conjunction with the occam programming
language.
The Helios Operating System - a hands-on workshop
=================================================
I. Graham (University of Waikato, New Zealand),
T. King & J. Powell (Perihelion Software / Distributed Software Ltd., U.K.)
Helios is a distributed operating system designed to run on MIMD
computers. Its Open System architecture provides complete parallel
programming support for both personal and super computers.
Since 1986, Helios has been chosen by most leading transputer
manufacturers as their preferred operating system. The key to this
success is its Unix environment and adherence to international standards
such as POSIX and X-Windows. Its programming support is comprehensive.
It includes a wide range of development tools, languages and networking
support.
The Helios tutorial provides a comprehensive overview of the product. The
morning session will cover the basic concepts of Helios and its tools, as
well as a practical workshop. During the afternoon, application case
studies will be described, followed by a discussion focussing on the
future direction of Helios.
Registration, Accommodation and Travel
======================================
Main conference 23-25 April including 3 nights hotel accommodation $650 US
All attendees who purchase the three night package must make
room reservations with Executive Meeting Management. All
rooms have two double beds and can sleep up to four occupants.
Main conference 23-25 April without hotel accommodation $450 US
Extra night's lodging booked through Executive Meeting Management $100 US
Additional night's lodging at TRANSPUTING '91 may be booked at
the specially discounted rate of $100.00 per night (including
state / local tax), through Executive Meeting Management only.
Student discount - deduct $225 US
Early registration before February 15 1991 deduct $100 US
(Only one discount allowable per person)
One 1/2 day tutorial/workshop on 22 April $100 US
Two 1/2 day tutorials/workshops on 22 April $150 US
Full-day tutorials/workshops on 22 or 26 April $150 US
Tutorial Identification - Please use the letters below to specify your
choice of tutorials on the application form.
A Communicating Process Architectures and Transputer Overview
B Formal Methods for Transputing
C Logic Programming on the Transputer
D Transputer Programming Environments (first half)
D Transputer Programming Environments (second half)
E Designing Parallel - Going Sequential
F Parallelizing Existing Code
G Mixed Language Programming on the Transputer
J Embedded Real-time Control Systems
K Real-time Kernels for C Programmers
L Designing Parallel - a hands-on workshop
M Image Processing - a hands-on workshop
N Scientific Computing
O Office Automation Applications
P Communications Applications
Q Artificial Intelligence
R The Helios Operating System - a hands-on workshop
Important Notes
Registration will be confirmed in writing. This MUST be presented at the
conference.
Registration cancellation must be confirmed in writing and a penalty of
10% of the paid registration fee will be assessed. No refund will be made
if cancellation is postmarked after 12th April, 1991. However,
registration (less the 10% assessment) can be applied towards a future
NATUG Program.
This conference meets the requirements for deductability under the new
Tax Reform; however, you should consult your own financial authority for
specific interpretation.
For additional program / lodging information, call Executive Meeting
Management at 1-800-828-7494 or (717) 731 9295. Staff, a message recorder
and a facsimile machine are available 24 hours a day.
Airline Travel Information
TRANSPUTING '91 has appointed Executive Meeting Management and American
Airlines as the official agency and air carrier for this meeting.
American Airlines will extend special conference rates to its hub in San
Jose, CA. A 40% discount on full day coach (7 day advance ticketing) and
5% discount on all published promotional fares.
For information on reduced airfare reservations and ticketing assistance,
call American Airlines Meeting Service Desk toll free at (800) 433-1790.
Ask for a special Meeting Saver Fare and indicate NATUG's STAR file
#SO1Z1L3.
International airfares are available through American Express. For more
information, contact American Express on phone +31 020-520-7777 or fax +31
020-623-4943.
-----------------------------------------------------------------------------
Registration Form - TRANSPUTING '91 World Conference
Sunnyvale, California, U.S.A., April 22 - 26, 1991
Please complete this page and mail with appropriate payment to :
Executive Meeting Management,
PO Box 434,
Camp Hill,
PA 17001
USA
Phone (717) 731 9295
Toll Free (800) 828 7494
Fax (717) 731 9295 and press * after beep
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-------------
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-------------
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-------------
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One half-day on 22nd April - $100.00 US
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