jacob@nydala.cs.umu.se (Peter Jacobsson) (03/04/91)
Last week I posted a request for material on simulators of
distributed memory computers.
These are the answers I have received.
I would like to thank all of you who responded.
From: Jesper Vasell <jesper@ce.chalmers.se>
N[r jag var p} SPDP90 (Symp. on Parallel and Distributed Processing)
i December s} tr{ffade jag en australiensare som hade utvecklat
n}gonting }t det h}llet. Hans namn och adress {r:
A.N. Pears
La Trobe University
Bundoora 3083
Australia
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From: " (Roland Ruehl)" <ruehl@iis.ethz.ch>
@inproceedings{K9,
author = "P. Beadle and C. Pommerell and M. Annaratone",
title = "{K9}: A simulator of distributed-memory parallel processors",
booktitle = "Proc. Supercomputing 89",
address = "Reno, Nevada",
organization = "ACM-IEEE",
page = "765-774",
month = "November",
year = "1989"}
----------------------------------------------------------------------
From: Marc Brandis <brandis@inf.ethz.ch>
K9 Simulator
Integrated Systems Laboratory
ETH-Zentrum, ETZ Building
CH-8092 Zurich
Prof. Marco Annaratone, email mxa@iis.ethz.ch
Claude Pommerell, email pommy@iis.ethz.ch
----------------------------------------------------------------------
From: tve@sprite.Berkeley.EDU (Thorsten von Eicken)
I'm starting to work on a similar thing. My goal is to be able to measure
the impact of changing architecture features on application performance.
In particular the network interfaces... My major goal is to be able to
simulate 1000 processors on a 1000 processors. I think that traditional
simulation won't do it. I'll have to `compile-in' the simulation stuff.
----------------------------------------------------------------------
From: Suresh Srinivas <ssriniva@iuvax.cs.indiana.edu>
I am working on some kind of a simulator too.
What I am trying to do, is to have a simulated environment for executing
parallel programs and experimenting with paradigms. At present, I am
trying to get an Actor based model to work.
----------------------------------------------------------------------
From: tyang@paul.rutgers.edu
T.H. Dunigan group at Roak Ridge National Laboratory, TN 37831
has developed one or two simulator(s) for message-passing
architecture (e.g. iPSC) in 1986.
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From: tiff@CS.UCLA.EDU (Tiffany Frazier)
Many of us at UCLA are using SIMON - which is exactly
what you describe.
Univ. of Utah - Fujimoto
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From: Jean-yves Colin <colinj@mist.CS.ORST.EDU>
In 1989, A.Joubert in France, built such a simulator, called SiGLe. It was
his PhD subject and the result was really interesting.
You could try to contact his co-author, F.Andre at 'andre@irisa.fr' (if
she still works there !).
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From: John.Willis@CS.CMU.EDU
Auriga is an experimental optimizing compiler translating
VHDL models (such as a multiprocessor) into a parallel simulation
running on a network of message-passing nodes.
----------------------------------------------------------------------
From: petter@idt.unit.no
Jeg brukte et halvt aar paa aa
simulere oppfoerselen av programmer skrevet i POOL, eksekvert paa
POOMA-maskinen, (for en introduksjon til begge se proceedings, PARLE
1989). Jeg har et paper om det som jeg kan sende deg dersom det er av
interesse, men dette er forholdsvis hoeynivaa simulering, og overser
detaljer som registerbruk, "peephole"-optimaliseringer etc.
Petter Moe
Department of Computer Systems and Telematics
The Norwegian Institute of Technology phone: +47-7-593470
N-7034 TRONDHEIM - NTH fax: +47-7-594466
NORWAY e-mail: petter@idt.unit.no
----------------------------------------------------------------------
From: ronald@ixstar.att.com (Ronald H Davis)
Jeffrey T. Kreulen and Matthew J. Thazhuthaveetil.
"Application-dependent Simulation of Microprocessor-based Multiprocessors"
Microprocessors and Microsystems. september 1990.
the authorsy are affiliated with pennsylvania state
university (usa)
----------------------------------------------------------------------
From: Miltos Dimitris Grammatikakis <mdgramma@uokmax.ecn.uoknor.edu>
1) L. G. Valiant, " Experiments with a parallel communication scheme ",
Proceedings of the 18th Allerton Conference on Communication, Control and
Computing, University of Illinois, October 1980, pp. 802-811.
2) L. Kleinrock, Communication Networks, Mc Graw Hill 1964.
3) M. Grammatikakis, S. Lakshmivarahan, and S. K. Dhall, "Experiments on
Probabilistic Routing for a Generalized Hypercube ", Proceedings of the
Workshop on Applied Computing 1989, pp. 131-133.
4) M. Grammatikakis, S. Lakshmivarahan, and S. K. Dhall, "Packet Routing for
Generalized Hypercube ", Proceedings of the 24th Annual Conference on Computer,
Information and Communication Systems, Princeton, NJ, March 1990, pp. 159-164.
5) M. Grammatikakis, "Probabilistic Routing Algorithms for Generalized
Hypercube", Proceedings of the 25th Annual Conference on Computer, Information
and Communication Systems, Baltimore, MD, March 1991 ( submitted ).
6) D. Nassimi and S. Sahni, " Optimal BPC Permutations on a Cube Connected SIMD
Computer ", IEEE Transactions on Computers, C-31 (4), April 1982 pp. 338-341.
As a last note let me say that I am simulating the star network and
connection machine. If you need a copy of 3,4,5, above let me know.
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From: haines@debussy.cs.colostate.edu (Matt Haines)
I know that there is an NCube simulator that runs on Sun's, but that's
about all.
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From: Claude.Jard@irisa.fr (Claude Jard)
I am working on simulation, and that for several years. We have designed
different kinds of simulator, all based on the Estelle description
language. The Estelle model (now an ISO standard for describing protocols)
is very closed to the model of Distributed Memory Parallel Computers like
iPSC if you look at the system level. Maybe too abstract for your purpose
but solves some problems for developing distributed programs.
References:
C. Jard, R. Groz, JF. Monin, Development of Veda: a Prototyping Tool
for Distributed Algorithms, IEEE tr. on SE, Vol14, no3, March 88.
C. Jard, JM, Jezequel, A Multiprocessor Estelle to C Compiler to
prototype Distributed Algorithms on Parallel Machines, proc. of the
9th IFIP int. symposium on Protocol Specification, Testing and
Verification, Twente univ., The Netherlands, North-Holland, June 89.
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From: u502sou@mpirbn.mpifr-bonn.mpg.de (Ignatios Souvatzis)
Contact Tom Dunigan at Oak Ridge National Laboratory (US of A),
<dunigan@msr.epm.ornl.gov>. He has an IPS/2 simulator for a single or
a net of homogenous workstations of BSD Unix systems.
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From: O A El-Ghajiji <O.A.E.El-Ghajiji@gdr.bath.ac.uk>
I am working on a parallel computer simulator as a part of my
Ph. d. research.
It will simulate a dataflow multiprocessor computer. The objectives
of the simulator is to obtain an approximate execution times for
a number of different algorithms by varying some hardware parameters.
Mr Otman A. El-Ghajiji
School of electrical engineering
University of Bath,
Claverton Down,
Bath Avon
United Kingdom.
eepoaeg@uk.ac.bath.gdr
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From: agn@Eng.Sun.COM (Andreas G. Nowatzyk)
I wrote several of those. Two of them are described in my PhD thesis,
"A Communication Architecture for Multiprocessor Networks", CMU-CS-89-181,
School of Computer Science, Carnegie Mellon University,
Pittsburgh PA 15213-3890, USA
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From: harrison@tcg.anl.gov
You may be interested in a set of tools (TCGMSG) that we
have developed
and been using for the last year.
TCGMSG is aimed at scientific applications in FORTRAN or C and strives
to provide a robust, portable and efficient message passing environment.
Robert J. Harrison
tel: (708) 972-7197
E-mail: harrison@tcg.anl.gov, harrison@anlchm.bitnet
letter: Bldg. 200, Theoretical Chemistry Group,
Argonne National Laboratory,
9700 S. Cass Avenue, Argonne, IL 60439.
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From: upchurch@hyper-gemini.Jpl.Nasa.Gov (Ed Upchurch)
I have done a considerable amount
of modeling and simulating distributed memory architectures
particularily hypercubes built here at CalTech and JPL.
I have detailed models of the Mark III and of the next generation of
our own adaptive routing/fault tolerant hypercube architecture.
The models use SES/workbench an easy to use graphical modeling language.
Dr Ed Upchurch
Jet Propulsion Lab
CalTech
4800 Oak Grove Drive
Pasadena, California 91109
(818) 354-8731
upchurch@hyper-gemini.Jpl.Nasa.Gov
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From: Roldan Pozo <roldan@tigger.Colorado.EDU>
We have a generic simulator that runs on any Unix box.
The simulator was developed by Oliver McBryan, the director of the
Center for Applied Parallel Processing, and handles iPSC/1, iSPC/2,
iPSC/860, and Caltech message primitives.
***********
***** ***** Roldan Pozo
***** ***** Center for Applied Parallel Processing
***** ***** and Department of Computer Science
***** ***** University of Colorado
***** ***** Boulder, CO 80309-430
***** *****
***** ***** Email: roldan@boulder.colorado.EDU
***** ***** Phone: (303) 492-7514
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From: cfleck@src.honeywell.com (Chuck Fleckentein)
You should talk to Bill Bain (Intel). He wrote the original
simulator for the iPSC/2.
He has his own company also:
Block Island Technologies
15455 NW Greenbrier Parkway Suite 210
Beaverton, Oregon 97006
(503) 690-7181
I believe his email address is wlb@isc.intel.com
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From: kitajima@alize.imag.fr (Joao Paulo Kitajima)
"This document describes the implementation and use of a self-driven
discrete event simulation model of a restricted class of MIMD (Multiple
Instruction stream Multiple Data stream) machine and a distributed
communicating sequential process program..."
The tool is very flexible because you can simulate not only
hypercubes, but any loosely-coupled architecture. Here goes the
pointer:
Skilling, Neil
Department of Chemical Engineering
The King's Buildings
University of Edinburgh
Mayfield Road - Edinburgh - EH9 1HA
e-mail: neil@uk.ac.ed.chemeng (I think that for UK you
have to change this order,i.e., neil@chemeng.ed.ac.uk)
tel: 031-650 4867
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From: loran@Eng.Sun.COM (Loran Ball)
Our simulator is written entirely in C and runs under Unix.
It simulates a set of modules that pass messages back and forth. Modules
can be anything but currently we have modules that together simulate
some of our systems. Some of the modules we have are:
SPARC processor
SPARC floating point unit
RAM
ROM
various MMU's
various buses (ex. Mbus, Sbus)
various I/O devices (serial, disk, etc)
loran@Eng.Sun.COM (Loran Ball)
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From: watro@linus.mitre.org
"Modeling Internode Communication For Hypercube Architectures" by
Upchurch and Neuse (SCS Summer Sim Conf, July 89). This paper is
based on communication in the JPL Mark III hypercube.trs@cs.city.ac.uk (Tom Stiemerling) (03/05/91)
Add to the list of distributed simulators my simulator of an MIMD shared memory design (called EPP1) on a transputer network. I simulated up to a 256 processor system on 128 transputers, and the simulator is written in Occam. The simulator is specific to this design though the same simulation methodology (parallel time-driven) is applicable to other simulations. A paper on simulator may appear in a special issue of the International Journal of Computer Simulation (this is uncomfirmed). Some of the results are presented in a technical report: "Combining in an MIMD shared memory multiprocessor simulation", EPCC-TR-90-09. Available from the Edinburgh Parallel Computing Centre, University of Edinburgh, JCMB, Kings Buildings, Mayfield Road, Edinburgh EH9 3JZ. UK. Thankyou for your attention. Tom.