pfluegl@chopin.eng.uci.edu (Manfred J. Pfluegl) (03/19/91)
Recently I had a chance to visit JPL/NASA in Pasadena. During
several discussions the name "DELTA-machine" was dropped. I never
heard anything about this system before but would like to read up
on it. DELTA seems to be a highly parallel architecture and I got
the impression that it was built by NASA. Can anyone give me
some references or tell me briefly the characteristics of this
system?
Any help is appreciated.
Manfred Pfluegl - believer of "Per Aspera Ad Astra"
***** ***** pfluegl@uci.edu (Internet)
* **** * **** pfluegl@uci.bitnet (Bitnet)
* ***** **** pfluegl%uci.edu@RELAY.CS.NET (Internet from Europe)
--
=========================== MODERATOR ==============================
Steve Stevenson {steve,fpst}@hubcap.clemson.edu
Department of Computer Science, comp.parallel
Clemson University, Clemson, SC 29634-1906 (803)656-5880.mabelljkubicky@tybalt.caltech.edu (Joseph J. Kubicky) (03/20/91)
pfluegl@chopin.eng.uci.edu (Manfred J. Pfluegl) writes: >Recently I had a chance to visit JPL/NASA in Pasadena. During >several discussions the name "DELTA-machine" was dropped. I never >heard anything about this system before but would like to read up >on it. DELTA seems to be a highly parallel architecture and I got >the impression that it was built by NASA. Can anyone give me >some references or tell me briefly the characteristics of this >system? >Any help is appreciated. > Manfred Pfluegl - believer of "Per Aspera Ad Astra" > ***** ***** pfluegl@uci.edu (Internet) > * **** * **** pfluegl@uci.bitnet (Bitnet) >* ***** **** pfluegl%uci.edu@RELAY.CS.NET (Internet from Europe) What I know about the Delta machine, which is what I've heard from Prof. Chuck Seitz in my VLSI class (his group designed the router chips for the mesh & did some other stuff with the machine), is this: - 2-D mesh (from some charts Seitz showed us last term, their simulations indicate this minimizes network latency over higher-dimension meshes) - 576 (I think) i860 processors - Something like 25-30GFLOPS peak performance - if you want, figure it out yourself: i860 rated at 66MFLOPS peak (that's single precision, I think - double around 40MFLOPS). Unfortunately, Intel used some creative benchmarking here - when you really look at the chip, you realize that the I/O bandwidth, even though it's got 64-bit data busses & a 128-bit wide on-chip D-cache, won't sustain 40MFLOPS for very long. Also, other features like parallel execution of scalar & FP ops is tricky (you've actually got to code the instructions such that the scalar opcode is in the lower 32 bits and the FP opcode in the top 32 bits). - Asynchronous router chips operate around 200MB/s bandwidth between a node & its four nearest neighbors. - Supposedly, we're getting it Spring term sometime. I'm sure if you play enough games with the code, you can actually squeeze something like 25 useful GFLOPS out of the machine. Sorry, but I know anything about an operating system (I imagine just a front end at first). Jay Kubicky jkubicky@cobalt.cco.caltech.edu -- =========================== MODERATOR ============================== Steve Stevenson {steve,fpst}@hubcap.clemson.edu Department of Computer Science, comp.parallel Clemson University, Clemson, SC 29634-1906 (803)656-5880.mabell
baird@trout.nosc.mil (John M. Baird) (03/20/91)
>From article <1991Mar18.162929.22688@hubcap.clemson.edu>, by pfluegl@chopin.eng.uci.edu (Manfred J. Pfluegl): > > Recently I had a chance to visit JPL/NASA in Pasadena. During > several discussions the name "DELTA-machine" was dropped. I never > heard anything about this system before but would like to read up > on it. DELTA seems to be a highly parallel architecture I know of a DELTA machine which is the Delta prototype version of the Intel iPSC/2 i860 based TOUCHSTONE parallel supercomputer. But the only version of it I knew was being delivered was a 532-node model for CalTech, so it may not be the same one. However, JPL and CalTech have close ties, so it may be the same machine. John Baird, Naval Ocean Systems Center, San Diego, CA USA -- =========================== MODERATOR ============================== Steve Stevenson {steve,fpst}@hubcap.clemson.edu Department of Computer Science, comp.parallel Clemson University, Clemson, SC 29634-1906 (803)656-5880.mabell
jdm@cs.wvu.wvnet.edu (James D Mooney,205K, 7,2913548) (03/20/91)
>From article <1991Mar18.162929.22688@hubcap.clemson.edu>, by pfluegl@chopin.eng.uci.edu (Manfred J. Pfluegl): > > Recently I had a chance to visit JPL/NASA in Pasadena. During > several discussions the name "DELTA-machine" was dropped. I never > heard anything about this system before but would like to read up > on it. DELTA seems to be a highly parallel architecture and I got > the impression that it was built by NASA. Can anyone give me > some references or tell me briefly the characteristics of this > system? > I was recently at an INTEL presentation in which this machine was described. The JPL DELTA is a large-scale version of INTEL's current iPSC hypercube series using i860 RISC processors. It is part of something called the "Touchstone" project. The Delta includes 528 i860 nodes connected in a 2-D fashion. It is said to achieve 32 GFlops peak performance. Processors operate in MIMD fashion with message-based communication and a single process per node. INTEL is still evolving their system architecture. Current iPSC systems are hypercubes with i860s and possibly 386s combined and usually no more than 32 - 64 nodes. The DELTA system is a unique installation. -- Jim Mooney Dept. of Stat. & Computer Science (304) 293-3607 West Virginia University Morgantown, WV 26506 INTERNET: jdm@a.cs.wvu.wvnet.edu -- =========================== MODERATOR ============================== Steve Stevenson {steve,fpst}@hubcap.clemson.edu Department of Computer Science, comp.parallel Clemson University, Clemson, SC 29634-1906 (803)656-5880.mabell
uselton@nas.nasa.gov (Samuel P. Uselton) (03/21/91)
The "delta" referred to in the previous posting is formally
DARPA's Touchstone Project, Delta Prototype.
It is a highly parallel machine, built by Intel, using i860 processors.
We have a Gamma prototype machine (one of two, the other went to Oak Ridge)
which is a preproduction version of what Intel Scientific is now selling as
the iSPC/860 - a cube architecture machine. Ours has 128 i860 procs
and 8 or 10 386's for I/O.
The Delta machine is supposed to have 512 i860's, and a different routing
architecture (ie NOT a cube). It is due to be delivered to JPL this
spring. We are supposed to get time on it, partly as comparison with the
Gamma.
Sam Uselton uselton@nas.nasa.gov
employed by CSC working for NASA (Ames) speaking for myself
--
=========================== MODERATOR ==============================
Steve Stevenson {steve,fpst}@hubcap.clemson.edu
Department of Computer Science, comp.parallel
Clemson University, Clemson, SC 29634-1906 (803)656-5880.mabellpriol@irisa.fr (Thierry Priol) (03/22/91)
>From article <1991Mar18.162929.22688@hubcap.clemson.edu>, by pfluegl@chopin.eng.uci.edu (Manfred J. Pfluegl): > > .... DELTA seems to be a highly parallel architecture and I got > the impression that it was built by NASA. Can anyone give me > some references or tell me briefly the characteristics of this IEEE Spectrum (january 91) have published some characteristics of the DELTA machine (Touchstone project). Thierry PRIOL -- Thierry PRIOL Phone: 99 36 20 00 IRISA / INRIA U.R. Rennes Fax: 99 38 38 32 Campus Universitaire de Beaulieu Telex: UNIRISA 950 473F 35042 RENNES CEDEX - FRANCE E-mail: priol@irisa.fr -- =========================== MODERATOR ============================== Steve Stevenson {steve,fpst}@hubcap.clemson.edu Department of Computer Science, comp.parallel Clemson University, Clemson, SC 29634-1906 (803)656-5880.mabell