zenith@ensmp.fr (Steven Ericsson Zenith) (04/16/91)
Ok, ok. So the H1 has finally been disclosed and I for one can breath a
sign of relief and stop biting my tongue so hard. But for all my history
with the H1 design team and Inmos I can't get the answer to one simple
question. It is this:
"What is the CPU overhead per word in a H1 block move?"
This was an unanswerable question when I left. In the Tx series it's 2
CPU cycles. Come on guys. Tell us if who've done something wonderful. On
a good day you'll tell me it's 0 cycles - that is, no address adjustments
are done by the CPU ;-) Great if it is! But what's the impact on the
memory subsystem (cache)? On the instruction pipeline? :-)
If anyone has attended the press announcements and recieved this
information can they please share it with me.
Oh. Why is this important? Well, on chip communication uses block move
instructions - if you're going to sell generalized message passing as
the "general purpose" way to program parallel machines - as Inmos
architects are doing and have done in the past (gulp, me included) -
then a lot depends on the answer to this question. Some of you will have
heard me mention the copy penalty before - well this is it.
Anyone wanna bet Occam 3 has some new data sharing mechanisms?
Steven
PS. From all the traffic recently I guess there are some UK and US
academics looking for jobs in Inmos marketing. Am I right?
--
Steven Ericsson Zenith <zenith@ensmp.fr>
Center for Research in Computer Science
Ecole Nationale Superieure des Mines de Paris. France
--
=========================== MODERATOR ==============================
Steve Stevenson {steve,fpst}@hubcap.clemson.edu
Department of Computer Science, comp.parallel
Clemson University, Clemson, SC 29634-1906 (803)656-5880.mabell