S.P.Lam@cs.bham.ac.uk (Steven Lam) (06/14/91)
Hi everybody, This is my first message to the group. Here I have a few questions waiting for your comment. 1. Can anyone tell me what is "Hypermesh"? 2. Is there anybody interested in having a new group for "Systolic Arrays"? Since there is already a Application Specific Array Processors Conference mainly on this architecture, it implies there is a significant interest in the topic. 3. I have developed a so-called "Two and an half dimensional Systolic Array" which basically consists of two tightly coupled mesh arrays. Thus, the third dimension only has two units. It's realizable on silicon wafer, especially with multiple substrate stacks or multiple level metallization. I have done an extensive investigation on the performance of this architecture in the areas of matrix algebra and digital signal processing. The emphasis of this archit. is on versatiliy, efficiency and cell utilization. It's been shown that the extra half dimension does give the desired features. Hope to hear from you soon. Stephen P.S. Lam -- =========================== MODERATOR ============================== Steve Stevenson {steve,fpst}@hubcap.clemson.edu Department of Computer Science, comp.parallel Clemson University, Clemson, SC 29634-1906 (803)656-5880.mabell