plouff@nac.dec.com (Wes Plouff - NAC LAN Engr 226-7423) (04/14/88)
Now that DMA peripherals are starting to show up (i.e. A2090), can anyone on the net give some guidelines on DMA timing in the Amiga. Specifically, what is the maximum recommended delay between bus request and bus grant? What is the maximum recommended time for an alternate master to keep the bus? Can the A2090 (any version) run into problems if it has to wait too long to get bus mastership? Pointers to official Commodore documentation are welcome. Thanks in advance, -- Wes Plouff | Ashes to ashes Digital Equipment Corp. | Dust to dust Littleton, Mass. | Let the rich man live plouff%nac.dec@decwrl.dec.com | And the poor man burst - or - ...!decwrl!nac!plouff | -- The Oyster Band
grr@cbmvax.UUCP (George Robbins) (04/21/88)
In article <8804132031.AA08782@decwrl.dec.com> plouff@nac.dec.com (Wes Plouff - NAC LAN Engr 226-7423) writes: > Now that DMA peripherals are starting to show up (i.e. A2090), can > anyone on the net give some guidelines on DMA timing in the Amiga. > > Specifically, what is the maximum recommended delay between bus request > and bus grant? What is the maximum recommended time for an alternate > master to keep the bus? Can the A2090 (any version) run into problems > if it has to wait too long to get bus mastership? I don't think we've ever published anything very specific about external DMA issues. The general rule is that you must make like a 68000 when doing your cycles - violations may fail immediatly, or later when somebody tries your device with a 68020 based system. BR / BG delays are system dependent -- could be a few clocks or many milliseconds, depending on video mode and blitter (nasty) activity. Maximum BG period should give some consideration to the system software's needing to get some cpu cycles on a screen synchronous basis. Relatively slow devices should implement fifo's or buffers rather than holding onto the bus waiting for data. I believe the A2090 typically issues 4-32 word bursts of DMA - the upper limit would recognize that the system *must* get some CPU cycles during a vertical interval, or the screen will glitch... -- George Robbins - now working for, uucp: {uunet|ihnp4|rutgers}!cbmvax!grr but no way officially representing arpa: cbmvax!grr@uunet.uu.net Commodore, Engineering Department fone: 215-431-9255 (only by moonlite)