[comp.sys.amiga.tech] blitter operation speeds

u563694848ea@deneb.ucdavis.edu (0040;0000008853;0;250;141;) (04/26/89)

Hi there,

	I'm currently working on blitter routines, (for that number one
amiga application which requires high speed graphics...) and would appreciate
some info as to how fast certain operations go.

Mainly, what is the difference in speed between doing a full A+B+C->D
blit and a simple A->D operation? Does the blit go faster if the
dma is turned off (reusing the same data) for one or two channels
in a A+B+C->D operation?

I don't need absolute speeds, percent offset from the A+B+C->D mode
would be perfect.

Thanks in advance - Bruce (When am I going to finish that damn game!) Rogers
(currently s110018@pollux.ucdavis.edu )

rokicki@polya.Stanford.EDU (Tomas G. Rokicki) (04/26/89)

> Hi there,

Howdy, howdy!

> Mainly, what is the difference in speed between doing a full A+B+C->D
> blit and a simple A->D operation? Does the blit go faster if the
> dma is turned off (reusing the same data) for one or two channels
> in a A+B+C->D operation?

Yep.  Simply stated:

   minimum cycle is 4 clocks (7.16MHz clocks)
   use of A always costs 2
   use of B is always free
   use of C or D is free
   use of C and D costs 2

So, we end up with the following table:

        Channel   Clocks/
        enabled   blitter
        A B C D   cycle
        -------   -------
        N N N N     4
        N N N Y     4
        N N Y N     4
        N N Y Y     6
        N Y N N     6
        N Y N Y     6
        N Y Y N     6
        N Y Y Y     8
        Y N N N     6
        Y N N Y     6
        Y N Y N     6
        Y N Y Y     8
        Y Y N N     6
        Y Y N Y     6
        Y Y Y N     6
        Y Y Y Y     8

Note that you still contend for DMA cycles, so these are maximum speeds.
Line mode always runs in 8-clock cycles.

-tom

rokicki@polya.Stanford.EDU (Tomas G. Rokicki) (04/26/89)

My mistake; the fifth through eighth lines should read:

         Channel   Clocks/
         enabled   blitter
         A B C D   cycle
         -------   -------
         N Y N N     4
         N Y N Y     4
         N Y Y N     4
         N Y Y Y     6

I type faster than I think . . .

-tom

rokicki@polya.Stanford.EDU (Tomas G. Rokicki) (04/26/89)

> My mistake; the fifth through eighth lines should read:

It gets worse.  Completely ignore my previous articles.  Here's the
scoop:

Minimum blitter cycle is four clocks (7.18MHz clocks.)
*A* is always free.
*B* always costs 2 cycles.
C or D is always free.
C and D costs two cycles.

Gotta get this right!

-tom