451061@UOTTAWA.BITNET (Valentin Pepelea) (06/16/89)
Mark Huth <mph@behemoth.phx.mcd.mot.com> writes in Message-ID: <11088@behemoth.phx.mcd.mot.com> > Current specs for '040 - released, not internal rumors - Oh, external rumors? > 68882 compatible FPU > Internal Harvard Architecture How about external architecture? Does it have separate data space and instruction space buses? I hope not, we're not ready for this. > On chip PMMU > Two 4k caches- in physical address space, simultaneously accessible > Two ATC - simultaneous address translation for data and instructions > Bus snooping for cache coherency > '030 object compatible > Concurrent FPU, IPU, MMU/BIU execution. > > Look for it in 25,33,50 and possibly 100 MHz versions. Prices? Valentin _________________________________________________________________________ "An operating system without Name: Valentin Pepelea virtual memory is an operating Phonet: (613) 231-7476 (New!) system without virtue." Bitnet: 451061@Uottawa.bitnet Usenet: Use cunyvm.cuny.edu gate - Ancient Inca Proverb Planet: 451061@acadvm1.UOttawa.CA
mph@behemoth.phx.mcd.mot.com (Mark Huth) (06/20/89)
In article <8906160412.AA09343@jade.berkeley.edu> 451061@UOTTAWA.BITNET (Valentin Pepelea) writes: > >How about external architecture? Does it have separate data space and >instruction space buses? I hope not, we're not ready for this. > Single logical bus; 32 bits data and address, not multiplexed. Sorry, you'll have to get your own pricing. Mark Huth