Valentin.Pepelea@JADE.BERKELEY.EDU (07/27/89)
In article <2105@hub.UUCP> dougp@voodoo.ucsb.edu writes: > > Is there any particular reasor that no microprocessor has limit > registors for the stack? How told you that? Actually, since this is a typical MMU function, indeed the 68851 PMMU as well as the 68030 and 68040 let you put limit restraints on addresses you wish to access. And they do it quite nicely too. Valentin _________________________________________________________________________ "An operating system without Name: Valentin Pepelea virtual memory is an operating Phonet: (613) 231-7476 (New!) system without virtue." Bitnet: 451061@Uottawa.bitnet Usenet: Use cunyvm.cuny.edu gate - Ancient Inca Proverb Planet: 451061@acadvm1.UOttawa.CA
mph@behemoth.phx.mcd.mot.com (Mark Huth) (07/28/89)
In article <8907270443.AA11716@jade.berkeley.edu> Valentin.Pepelea@JADE.BERKELEY.EDU writes: >In article <2105@hub.UUCP> dougp@voodoo.ucsb.edu writes: > >> >> Is there any particular reasor that no microprocessor has limit >> registors for the stack? > >How told you that? Actually, since this is a typical MMU function, indeed >the 68851 PMMU as well as the 68030 and 68040 let you put limit restraints >on addresses you wish to access. And they do it quite nicely too. This seems a bit disingenuous as a response to the question. The PMMU family from Motorola does not have address limit capability in the sense that seems to be implied in the response. The old segmenting MMU from Motorola (68451, I believe) did, but the new stuff doesn't. Thus, the only way that the PMMUs will provide stack limit protection is for stacks that are integral pages in both size and location. The PMMU allows power of two page sizes from 2^8 through 2^15. Additionally, since stack operations are not distinguishable from other memory access operations, stack pages would need to be logically non-contiguous with other program data memory areas, placing constraints on the memory model used by compilers, linkers, and loaders. While it is possible to use the Motorola PMMUs to provide stack limit checking, given that the rest of the system is designed with that in mind, the protection is indirect. It also will not guard against such things as a lea blah,sp moving the stack pointer out of bounds, but into another program accessible data area. I therefore conclude that the use of the PMMU with the 680x0 processor family can provide some, but not all, of the functions that would be provided by stack limit registers. Mark Huth