hsplab (02/12/83)
Approximately 2 years ago, I designed a AMD9511 into a computer system and had significant timing problems. It appeared that the timing diagrams provided by AMD did not correlate well with the actual behavior. In addition the chip allowed accession of the stack in such a manner that it was **very** difficult to detect that somehow the process of reading the stack did not advance the stack. I finally worked the problems through by significantly lengthening the access times for reads/writes. I was distressed by the fact that I could not depend on the chip itself to provide me with the proper status signals even though the AMD literature seemed to allow it. I am fasinated by the experience others have had with the AMD chips. I had assumed that the problems I had were related to my inexperience with the chip itself. David Chou Univ of NC, Chapel Hill