ins425v@monu4.cc.monash.edu.au (mr t.h. mackenzie) (06/01/90)
Perhaps this has been discussed earlier but I have only just been given access to the news network. Does anyone know how to get an Amiga 500 with a Rev 6 board running with 1MEG chip ram AS WELL AS the A501 memory expansion. The second 1/5 Meg of the chip ram (when it is installed) runs off the same _RAS1 line as the A501. I currently have a circuit to split the _RAS1 line (Combining the A19 and A23 lines into A19 of Obese Angus so it responds to both) using the _RAS1 line, the _RAS0 line (to detect refresh for the A501 which only has 41256 rams), the _RAMEN line from Gary to decide whether Angus or the processor is initiating the access, (I have also tried using _BLIT for this), and A19 , A23 to decide on which set of ram. So far I have (with circuit Rev3) succeeded in letting the processor have access to both sets of ram, but when angus tries to access the ram on it's own behalf the machine crashes. (Evidently the RAS1 is delayed too long by the extra decoder circuitry so that the ram does not have the required 15ns between _RAS and _CAS) My current decoder has a delay time of approximately 8 ns using Fast TTL. The circuit MAY work if this can be decreased to 4ns (This may be possible with Fast TTL open collector OR gates, but I cannot get these!) The Circuit: A19(Obese Angus) = A19 + A23 _Refresh = _RAS1 + _RAS0 _UpperChip = _BLIT + _RAS1 OR !_RAMEN + _RAS1 (I have tried both) _ChipRAS1= _Refresh._UpperChip.(_RAS1 + !A19) _FastRAS1 = _Refresh.(_RAS1 + !A23) These last 2 signals are passed to the appropriate ram bank via the 74F244 already on board. (It has 2 spare lines) Note that this is working. (I have a software fix to convert 0x80000..0x100000 to fast ram so Angus doesn't do anything to it.)
geoff@actrix.co.nz (Geoff McCaughan) (06/06/90)
In article <2400@monu1.cc.monash.oz> ins425v@monu4.cc.monash.edu.au (mr t.h. mackenzie) writes: >Does anyone know how to get an Amiga 500 with a Rev 6 board running with >1MEG chip ram AS WELL AS the A501 memory expansion. The second 1/5 Meg of the >chip ram (when it is installed) runs off the same _RAS1 line as the A501. > >The Circuit: >A19(Obese Angus) = A19 + A23 >_Refresh = _RAS1 + _RAS0 OK, you got this bit right!! >_ChipRAS1= _Refresh._UpperChip.(_RAS1 + !A19) >_FastRAS1 = _Refresh.(_RAS1 + !A23) OK, here's how I did it: NAND _BLIT and A23, pass this to the D input of a D type flipflop. Clock the flipflop with _CDAC. AND the Q output of the flipflop with _RAS1 for _RAS1FAST and AND _Q with _RAS1 for _RAS1CHIP (as these are active low signals, AND them with OR gates). Now OR the resulting signals with _REFRESH (using AND gates natch). The you can achieve the same logic with just the NAND gate and an inverter but it doesn't work, the secret is using _CDAC and the flipflop which ensures we never change state during a _RAS cycle. I have been using this hack for a couple of months now and can't break it. I have also done it to a Rev 5 board (by piggybacking the RAM in the A501). I have written up instructions for this hack along with a circuit diagram for out local Amiga newsletter, so if you want a copy, let me know your snail address. I guess if there's enough interest I could post it on the net [ if I can figure out how to do that 8-) ] Cheers!