hawk@pnet01.cts.com (John Anderson) (08/25/90)
I've been following the discussions (or lack there of) on hacking the 2000 a bit to get the 2 meg agnus to work in it. Cost is of no importance so even if the PLCC (or something like that) piggy back sockets are $120 each, that doesn't matter. Dave Haynie, if you have any info that I might need then please let me know. I have the schematics of the 2000 and the 1 meg agnus in my B2000. If I can get a copy of the 3000 schematics, will that be enough info to convert the pins from the 1 meg agnus to the way they are supposed to be on the 2 meg version? A quick question (or two): are there the same number of pins on the 1 meg agnus that are on the 2 meg agnus, and if yes then: what happens to the lines that are converted? If anybody else has any information that can be of help then please let me know. Thanks ahead of time.
uzun@pnet01.cts.com (Roger Uzun) (08/25/90)
I believe some signals that were internal to the old agnus have been brought
out or vice versa, so it was said that additional hardware would be required,
you cannot just redirect the pinout of the new agnus to sockets on the old
(2000) motherboard, I imagine you have to cut a trace on the motherboard
to get at some/insert some required signal.
-Roger
UUCP: {hplabs!hp-sdd ucsd nosc}!crash!pnet01!uzun
ARPA: crash!pnet01!uzun@nosc.mil
INET: uzun@pnet01.cts.comppessi@niksula.hut.fi (Pekka Pessi) (08/25/90)
>>>>> On 25 Aug 90 05:16:09 GMT, uzun@pnet01.cts.com (Roger Uzun) said: > I believe some signals that were internal to the old agnus have been brought > out or vice versa, so it was said that additional hardware would be required, > you cannot just redirect the pinout of the new agnus to sockets on the old > (2000) motherboard, I imagine you have to cut a trace on the motherboard > to get at some/insert some required signal. I think that XCLK signal can be ignored if you do not use Genlock. Additional circuitry in A3000 consists of 2 PALs and 3 FFs, but I think it can be reduced to a couple TTL:s if you do not want 32-bit interface to CHIP-memory. -- ppessi@niksula.hut.fi ! M{ kaunehin oon tel +358 0 455 4757 ! ja tied{nkin sen JMT 11E122; 02150 Espoo ! ja siks' m{ Mua aina aattelen - Pekka Pessi
d6b@psuecl.bitnet (08/26/90)
In article <4093@crash.cts.com>, hawk@pnet01.cts.com (John Anderson) writes: > I've been following the discussions (or lack there of) on hacking the 2000 > a bit to get the 2 meg agnus to work in it. Cost is of no importance so even > if the PLCC (or something like that) piggy back sockets are $120 each, that > doesn't matter. Dave Haynie, if you have any info that I might need then > please let me know. I have the schematics of the 2000 and the 1 meg agnus in > my B2000. If I can get a copy of the 3000 schematics, will that be enough > info to convert the pins from the 1 meg agnus to the way they are supposed to > be on the 2 meg version? A quick question (or two): are there the same number > of pins on the 1 meg agnus that are on the 2 meg agnus, and if yes then: what > happens to the lines that are converted? If anybody else has any information > that can be of help then please let me know. Thanks ahead of time. I don't have detailed information, but I've picked up some general info. RAS1* no longer exists. A "MA9" (or something like that) has been added. In other words, the "natural" configuration for the 2MB Agnus is a single bank of 1M by 1 DRAMs (the 3000 has extra logic to control its two banks -- needed to get 32 bits out at a time). Also, another address line is conected (A20). That presents a problem: one more pin is used than with the 1MB Agnus. As a person who knows nothing about chip design, I'd say they should have ditched one of those redundant power/ground lines, but I guess their layout requires those. To get the extra pin (2 actually; I guess one is unused) they ditched the XCLK logic used by Genlocks (specifically, XCLK and XCLKEN*). It's implemented by some rather trivial external logic on the 3000 (and of course the 1000 as well). Hope this helps a little... -- Dan Babcock Note my new addresses... Mail ("forever"): P.O. Box 1532 / Southgate, MI 48195 Mail (school): Atherton Hall Room 63 / University Park, PA 16802 Internet: D6B@ECL.PSU.Edu Bitnet: D6B@PSUECL.Bitnet (capitalization is probably wrong) Voice: (814)-862-2931