t-krgr (02/28/83)
The recent flurry of activity in net.micro about the NS16000 series chip set has been a nice surprise, especially to members of the 5 or 6 project teams at various companies endeavoring to put up UNIX ports to the chip set. Although some of the details have been scant or occasionally outright wrong, the information in net.micro of late about the NS16000 series has been generally correct. If you've gotten the impression that the NS16032 is a lot like a VAX, has very small packaging, and is relatively inexpensive - you have the essence of the product's characteristics. It's not hard to decide what you think of the architecture if you see the technical details; I find that most opinions are usually either unconvinced mild interest or wild enthusiasm, depending on the reviewer's background and/or vested interests. Instead of repeating information from the technical data sheets, I think the most helpful thing to do here will be to give the names of the major documents, with some commentary and suggestions for the curious. >From National Semiconductor, there are fairly clear technical data sheets plus a programmer's manual: NS16032S-6, NS16032S-4 High Performance Microprocessors November 1982 > machine and instruction set architecture > hardware timing > general description of MMU architecture and timing > trap handling > general description of interrupt handling using the related 16202 Interrupt Control Unit > instruction formats > not sufficient information for programming (see programmer's reference below) NS16082 Memory Management Unit March 1982 > architecture > hardware timing > paging / address translation details NS16202 Interrupt Control Unit October 1982 > vectored interrupts > cascading of ICU's > priority modes NS16201 Timing and Control Unit NS16081 Floating Point Unit October 1982 > brief, general information NS16000 Programmer's Reference Manual February 1982 Order #420306565-001 > the whole story for the instruction set > sufficient information for programming On these documents, NS gives their address as: NSC 2900 Semiconductor Drive Santa Clara, CA 95051 408-737-5000 --------------------------------------------------------------------------- Now for the fun part (commentary & scuttlebutt)... Things to look for (+ for good, - for not-so-good, ! for big surprises): +! Physical size of the chips. Compare with your favorite micro for a pleasant surprise. These chips can be crowded together pretty well, leading to some interesting implications for small systems. Below is a pictorial representation IF you have displayed/printed it at 10 char/in horizontal, 6 lines/in vertical: +----------------------+ | 16032 | approx. 2.4 x 0.6 inches | CPU | 48 pins +----------------------+ +-----------------------+ | 16082 | approx. 2.7 x 0.6 inches | MMU | 48 pins +-----------------------+ +------------------+ | 16202 | approx. 2.0 x 0.6 | ICU | 40 pins +------------------+ +----------+ | 16201 | approx. 1.2 x 0.6 inches | TCU | 24 pins +----------+ +----------+ | 16201 | approx. 1.2 x 0.6 inches | FPU | 24 pins +----------+ + 'mostly' orthogonal addressing. Almost all instructions use all addressing modes, exceptions are few and clear. + is a very nice machine for UNIX, mostly due to similarity with VAX instruction set architecture (read on...) ! was not originally intended to necessarily be a nice machine for UNIX! This was to be a hot Pascal machine, or so the story goes... which leads to - - in a UNIX / C environment, some of the architecture is vestigial. Take a close look at the CXP/RXP instructions (1 operand mode, slow performance), based access of data (static base register), and the whole Module Table / Link Table external reference architecture. These items just don't fit UNIX & C; some developers are dropping support for these features, or are omitting them in the first place for UNIX implementations. ? what real (repeat REAL) opportunities are there for dynamic linking, using the MT/LT external reference architecture? + a slave processor architecture is used among the CPU, MMU, & FPU, and allows for a custom slave processor (opcodes already implemented in the CPU) +! reference bit in the MMU, a step up from VAX. Raises some interesting issues for those thinking of bringing over BSD paging unmodified. - MMU adds 1 cycle to the fixed 4 cycle memory access time by the CPU + MMU cache for page table entries +! MMU support for instruction trace and breakpoint + ICU cascade architecture + ICU priority modes (fixed, auto-rotate, special mask, polling) +! FPU performance (at 10 MHz rate) (advertised values) 32-bit 64-bit add 7.4 7.4 mult 4.8 6.2 div 8.9 11.8 - not enough information on the FPU instruction formats ?? performance, an issue not yet clear. The numbers add up to indicate very good performance, especially in a UNIX environment. Yet look at the unofficial benchmark figures recently published on the net, or better yet, sit down and use one at a trade show. I think we'll see the same range of performance and improvement over time in the NS16000 category as we've seen for 68000's (which show a very wide variation in performance). The jury is still out, but indications are good. ?? delivery. Sample quantities have been available for months, but the real question is the availability in commercial quantities of the 10MHz parts, since they are (in my opinion) least necessary to give the 68000 high-speed parts significant competition. There is a reasonable expectation on the part of some NS customers that volume deliveries of these parts will begin this 'summer' (a direct quote from NS, who will not elaborate). Remember, the 16032 competes with the 68010, not 68000, so the timing of volume shipments of each are certainly going to be a big factor in the contest. +,- getting started. A multibus-based card is available from NS (DB16000) for the curious. If you are going to get serious about using that setup, DEFINITELY talk to someone who has done it already. Don't be a pioneer. ... miscellaneous ... The 16032 will compete with the 68010. The 32032 will compete with the 68020. Comparisons of the 16032 with non-virtual architectures is not apples-apples. With volume shipments of 68010 still in the future, is the 16032 truly 'late to market'? I don't know. Among the ports of UNIX in various stages of completion are those by: TSI (System III, later System V with paging added, to be released this summer) NS (BSD; to be revamped to recognize above mentioned vestigial 16032 characteristics) HCR (BSD; same as NS?? hard to tell; their videotaped presentation at UNICOM showed a NS Mesa(!) computer system. at least two others, whom I think I'm not able to mention by name Expect the division into BSD and non-BSD (ATT) camps, the same way things seem to have gone with 68000 and other ports. The 16032 is 32-bit internal, 16-bit external; it appears that the intention is for an easy move to the 32032 (full 32-bit). Will the 68020 be as easy a step? It appears that the FPU instructions will directly operate on memory, but the documentation is not totally clear on that. Don't confuse 16032-related stuff with the NCR 16/32 Tower, I am pretty sure they don't use the NS chip set. Cross-development software is available; obviously the above- mentioned companies are a starting point for leads there. More than the usual C/Pascal/Fortran will be available. Mainframe grade compilers for those languages plus PL/I-G, Basic, and RPG-II are in the works. Especially in the case of PL/I, there may be some interesting implications for applications software. In summary, the chip set deserves (and is getting) a lot of consideration for use in new systems. The repertoire of NS16000-based systems is rather limited right now, but won't be for long - which will put many designers and customers in the position of needing to know a lot about the chip. Conclusion: get started early. Michael Krueger Translation Systems, Inc. 138 Brighton Ave. Allston, MA 02134 (Boston) 617-254-3482