martin@IRO.UMontreal.CA (Daniel Martin) (10/09/90)
I tested the speed of an A3000/25 MHz + Aztec v3.6 with the dhrystone v2.1
program. I enclosed the dhrystone program test loop with a Forbid() - Permit()
pair. The results, using a stopwacth, small code (16 bit ints) and using only
c.lib was around 6000 dhrystones (i.e 30000 loops in around 5 seconds). I used
cache and burst for data and instruction (setcpu 1.6).
When the program was run without fast ram available (say 800k CHIP, 3k FAST)
those numbers fell to around 1760 dhrystones, (i.e. 30000 loops in around 17
seconds).
Why is there such a speed decrease (more than 3x)?
--
// Daniel Martin Universite de Montreal \\
// MediaLab, ca vous regarde! C.P. 6128, Succursale A, \\
\\// Mail: martin@IRO.UMontreal.CA Montreal (Quebec), CANADA, \\//
\/ Tel.: (514) 343-6111 poste 3494 H3C 3J7 \/navas@cory.Berkeley.EDU (David C. Navas) (10/13/90)
In article <1990Oct9.042900.8479@IRO.UMontreal.CA> martin@IRO.UMontreal.CA (Daniel Martin) writes: > > I tested the speed of an A3000/25 MHz + Aztec v3.6 with the dhrystone v2.1 > > Why is there such a speed decrease (more than 3x)? Correct me if I'm wrong, but I thought that you had to synchronize with the CHIP memory for every access request.... That might explain it. [CHIP RAM accessed by chip memory at 7Mhz, and while the A3000 looks at that memory as 32 bit, I thought it could only look at it at that speed?] or it could be bad luck. :) David Navas navas@sim.berkeley.edu "Excuse my ignorance, but I've been run over by my train of thought." -me
daveh@cbmvax.commodore.com (Dave Haynie) (10/16/90)
In article <28741@pasteur.Berkeley.EDU> navas@cory.Berkeley.EDU writes: > >In article <1990Oct9.042900.8479@IRO.UMontreal.CA> martin@IRO.UMontreal.CA (Daniel Martin) writes: >> >> I tested the speed of an A3000/25 MHz + Aztec v3.6 with the dhrystone v2.1 >> Why is there such a speed decrease (more than 3x)? >Correct me if I'm wrong, but I thought that you had to synchronize with the >CHIP memory for every access request.... That might explain it. >[CHIP RAM accessed by chip memory at 7Mhz, and while the A3000 looks at that > memory as 32 bit, I thought it could only look at it at that speed?] Well, basically. It doesn't make sense to speak of memory in terms of MHZ, since it isn't really clocked, per se. The Chip memory in the 3000, like in any Amiga, runs 560ns memory cycles. Since the clocks that define the Chip memory cycle aren't related to the 68030 clock in the 3000, there may also be a synchronization delay, where some additional time must be added to get the CPU and the memory into the proper state to communicate with one another. Then there's the fact that, while the Chip memory cycle is 560ns, you have to pick the right half of the cycle to start with it, otherwise there's an additional wait during the Chip half of the cycle. This resynchronization which the Chip bus also happens on 68000 based Amigas, but it's more likely to occur. Fast RAM, on the other hand, runs a 200ns cycle on a 25MHz Amiga. With burst mode, the effective time turns out to be 110ns per 32 bit fetch, and there are no synchronization delays of either kind found on the chip bus. So after a fashion, the Fast memory is between 5 and 8 times faster than Chip memory. And that's even before you start any heavy Denise or blitter/copper activity. >David Navas navas@sim.berkeley.edu -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Standing on the shoulders of giants leaves me cold -REM