don@brahms.udel.edu (Donald R Lloyd) (11/09/90)
I've been looking for information on the various type of RAM for a week
or so, (more out of curiosity than out of any real need to know), and so
far have found only what I already knew:
DRAM is relatively slow & has to be periodically refreshed
static RAM is fast & needs no refresh
I also found brief mention of "pseudo-static RAM" (in Tannenbaum's
"Stuctured Computer Organization", 3rd edition), which is basically
dynamic RAM with some refresh circuitry on-chip (?).
Questions:
Why is DRAM slower than SRAM? I can't see how having to refresh it
would cause any tremendous slowdown.
What is static column RAM? I've been told it's the same as static
RAM, but that doesn't seem right (otherwise the 3000 would be
a good bit faster and a good bit more expensive). Is it the
equivalent of what Tannenbaum calls pseudo-static?
What about VRAM? Somehow specially designed for video memory, or
just some marketer's way to make the static RAM on a video card
sound superior?
While I'm at it, why are ROMs inherently so slow?
Why is there air?
How many licks does it take to get to the center of a Tootsie Pop?
Where's my free 68040 upgrade for the 3000 I just ordered?
Thanks for any info you can provide.
--
Gibberish Soon to be Amiga 3000 owner/fanatic! (I hope)
is spoken Contact don@brahms.udel.edu for more information.
here. DISCLAIMER: It's all YOUR fault.252u3130@fergvax.unl.edu (Phil Dietz) (11/09/90)
In article <15571@brahms.udel.edu> don@brahms.udel.edu (Donald R Lloyd) writes: > > I've been looking for information on the various type of RAM for a week >or so, (more out of curiosity than out of any real need to know), and so >far have found only what I already knew: > > DRAM is relatively slow & has to be periodically refreshed > static RAM is fast & needs no refresh > I'm not too sure that TRUE statis rams are faster. In my book Computer Organization (Hamacher Vranesic Zaky ver 3 pg 322) it quotes "MOS transistors are higher-impedence devices; they yield circuits that have lower power dissipation. Their disadvantage is their slower speed of operation." > I also found brief mention of "pseudo-static RAM" (in Tannenbaum's >"Stuctured Computer Organization", 3rd edition), which is basically >dynamic RAM with some refresh circuitry on-chip (?). > Questions: > Why is DRAM slower than SRAM? I can't see how having to refresh it > would cause any tremendous slowdown. > Well, everything takes time. It may only take nanoseconds to refresh the RAM, but it is ALWAYS refreshing the RAM. The time slowly but surely adds..... Also looking at a DRAM schematic, I notice that the DRAM has a Timing control segment that is connected to the Refresh Control and Refresh counter modules....All this stuff to keep track of what SRAM already does without. I guess all this EXTRA stuff really burdens the speed... > What is static column RAM? I've been told it's the same as static > RAM, but that doesn't seem right (otherwise the 3000 would be > a good bit faster and a good bit more expensive). Is it the > equivalent of what Tannenbaum calls pseudo-static? > > What about VRAM? Somehow specially designed for video memory, or > just some marketer's way to make the static RAM on a video card > sound superior? In Computer Organization it quotes: "<About DRAM> The faster rate attainable in block transfers can be exploited in specialized machines in which memory accesses follow regular patterns, such as GRAPHICS TERMINALS. This feature can also be benefitial in general-purpose computers for the transfer of data blocks between the main memory and a cache...." > > While I'm at it, why are ROMs inherently so slow? > > Why is there air? > > How many licks does it take to get to the center of a Tootsie Pop? One big one. :) > > Where's my free 68040 upgrade for the 3000 I just ordered? > > Thanks for any info you can provide. > > >-- > Gibberish Soon to be Amiga 3000 owner/fanatic! (I hope) > is spoken Contact don@brahms.udel.edu for more information. > here. DISCLAIMER: It's all YOUR fault. Phil Dietz <<<=================--------- Cheap Ad ---------===================<<< Phil Dietz SWL Lincoln 565 MEGS! 2 lines 252u3130@fergvax.unl.edu (402)421-1963 AMIGA, IBM, MAC, GIFS IBM'ers and Mac'ers are shopping for a life. Amiga the best!
leblanc@eecg.toronto.edu (Marcel LeBlanc) (11/09/90)
252u3130@fergvax.unl.edu (Phil Dietz) writes: >In article <15571@brahms.udel.edu> don@brahms.udel.edu (Donald R Lloyd) writes: >> >> I've been looking for information on the various type of RAM for a week >>or so, (more out of curiosity than out of any real need to know), and so >>far have found only what I already knew: >> >> DRAM is relatively slow & has to be periodically refreshed >> static RAM is fast & needs no refresh >> >I'm not too sure that TRUE statis rams are faster. In my book Computer >Organization (Hamacher Vranesic Zaky ver 3 pg 322) it quotes > >"MOS transistors are higher-impedence devices; they yield circuits that >have lower power dissipation. Their disadvantage is their slower speed >of operation." The vast majority of static RAMs available today are CMOS devices, so it's not the device technology that is responsible for the speed difference here. The primary reason DRAMs are slower than SRAMs is found in the design of the memory cell. DRAMs implement "memory" by storing charge on a capacitor, whereas SRAM uses an active circuit (transistors with feedback - yes I'm simplifying). When the gating transistor of a DRAM cell is enabled (i.e. when that bit is read), only the charge stored in the capacitor is available to change to state of the bit line. Since the capacitance of the cell is very small compared to the capacitance of the bit line, sense amplifiers must be used to detect the small change in voltage on the bit line. The memory cell in SRAMs consists of an active circuit of 4 transistors (for CMOS) that can drive the bit line much more quickly than the minimally sized capacitor can. The active circuit (i.e. it's connected to the power supply) is responsible for both the faster response time and the freedom from refresh. Also, DRAM bit lines must be "pre-charged" to a reference value before the memory cell is read so that the sense amps will properly detect the voltage change when the charge of the memory capacitor is added to the bit line charge. This is why 'access time' is only half the story with DRAMs. Well, this is getting a little long, so I'll stop here. >> I also found brief mention of "pseudo-static RAM" (in Tannenbaum's >>"Stuctured Computer Organization", 3rd edition), which is basically >>dynamic RAM with some refresh circuitry on-chip (?). >> Questions: >> Why is DRAM slower than SRAM? I can't see how having to refresh it >> would cause any tremendous slowdown. > >Well, everything takes time. It may only take nanoseconds to refresh >the RAM, but it is ALWAYS refreshing the RAM. The time slowly but >surely adds..... But in a good design, refresh amounts to very little time. Dave Haynie recently answered somebody's question asking how often refresh occured (although in that case it was a question related to the power consumption of an expansion board with excessive refresh). Since he will certainly read this :-), maybe he will post those minimal refresh rate numbers again. I would have to look them up. >> While I'm at it, why are ROMs inherently so slow? They aren't. A chip designer makes tradeoffs between density and speed. If you are targetting maximum density, then you will certainly be sacrificing speed. You can buy ROMs that are as fast as very fast SRAM, but don't expect to find either of these in 1 Mbit sizes. (yeah I know you can buy 1 Mbit SRAM, but I said *very fast*!) Not that long ago I commented on the cost or ROM vs. RAM, and I questioned the wisdon of ever instaling Kickstart on ROM in the A3000. Although Dave H. said that ROM was less expensive than RAM, I still question this. The only way ROM is going to be less expensive than RAM is if you have huge volumes! I know I won't get a direct answer from Commodore, but can the volume numbers for the A3000 possibly justify this? Like I said, I still don't believe this. >> Where's my free 68040 upgrade for the 3000 I just ordered? Probably lost with my free 68040 upgrade. Marcel A. LeBlanc -- Electrical Eng. Computer Group, Univ. of Toronto ----------------------------------------------------------------------- leblanc@eecg.toronto.edu else: uunet!utcsri!eecg!leblanc
kdarling@hobbes.ncsu.edu (Kevin Darling) (11/09/90)
Don asks (and durn it, I wrote up a long, detailed message about this
with full specs on CIS a while back, but I cannot find it on disk now):
> What is static column RAM?
Ok. Simplified, dynamic RAM is divided into "rows" and "columns" (a matrix),
as I'm sure you've read by now. A 1-meg chip is 1024 rows by 1024 columns.
To access a bit, you normally give the ram chip the row address first,
and then the column address, via the same shared address input pins.
And so that the chip knows which is which (row vs column), you also use two
extra pins... Row Address Strobe (RAS) and Column Address Strobe (CAS).
Address: row col row col (two memory accesses)
RAS* ---__________---__________ normal dram mode
CAS* --------_____--------_____
Data xxx xxx
DRAM access timing is composed of many specs, but one main delay is in
how quickly RAS can be strobed up and down (again, simplified). So ram
makers came up with an enhancment often called "page mode", where RAS
can stay low while just CAS strobes (obviously this only works as long
as the "row address" doesn't change!)... which speeds things up:
Address: row col col (two memory accesses)
RAS* ---__________________ page mode
CAS* --------_____---_____
Data xxx xxx
And we also have Static Column mode, which allows the column address to
change w/o CAS*, yet the data output follows correctly (like "static" ram):
Address: row col col (two memory accesses)
RAS* ---_________________ static column mode
CAS* --------____________
Data xxx xxx
The A3K can use either paged or column. But while Static Column can be a
tiny bit faster, my home timing analysis indicated that it wouldn't make
any diff which one you used on the 3000. I've heard otherwise, so I'd
be interested to know, from the good CBM folk, what the real deal is. Thx!
PS: there are lots of kinds of VRAMs. Basically, they take advantage of
video data always coming out in sequential order, and have other neat tricks.
Kevin Darling - "This is your | CIS: 76703,4227 Delphi:OS9ugpres
brain. This is your brain on | Inet: 76703.4227@compuserve.com (best)
non-Motorola cpus. Got it?" ;-)| or: kdarling@hobbes.ncsu.edudillon@overload.Berkeley.CA.US (Matthew Dillon) (11/09/90)
In article <15571@brahms.udel.edu> don@brahms.udel.edu (Donald R Lloyd) writes: > > I've been looking for information on the various type of RAM for a week >or so, (more out of curiosity than out of any real need to know), and so >far have found only what I already knew: > > DRAM is relatively slow & has to be periodically refreshed > static RAM is fast & needs no refresh The fastest reasonably priced (and available in quantity) static RAM runs on the order of 20ns these days. The fastest reasonably priced DRAM (and available in quantity) is 80ns. 80ns DRAM = 80ns page mode / static column access, 160ns random access. So, for random accesses static RAM runs about 8 times faster. DRAM has about 4 times the storage capacity for equivalent chip areas, due to requiring four transistors per cell. A DRAM requires only one transistor and a capacitor. STATIC RAM uses a completely static design and thus takes very little power... picowatts in standby mode (I am assuming CMOS here, of course), whereas DRAM requires refresh and takes a lot of power even when 'idle'. The REFRESH required for DRAM takes less than 1% of the available bandwidth ... you basically do not notice it. It does complicate your board design, though if you use an existing DRAM controller it does not. STATIC RAM requires more PINS than DRAM due to the way addressing works. DRAM chips are thus a lot smaller (fewer pins). > I also found brief mention of "pseudo-static RAM" (in Tannenbaum's >"Stuctured Computer Organization", 3rd edition), which is basically >dynamic RAM with some refresh circuitry on-chip (?). Essentially. I would not touch pseudo static RAM with a 10-foot poll personally. > Questions: > Why is DRAM slower than SRAM? I can't see how having to refresh it > would cause any tremendous slowdown. Static RAM is basically combinational logic all the way to the memory storage cell. You put an address on the bus and X ns later you can drive the WR line, or Y ns later the results of a read will have propogated back. No clocking is required. DRAM requires a two phase address cycle. For a full random access you drive the address lines with one half the address and then bring RAS low. You then drive the address lines with the other half of the address and bring CAS low. You hold CAS for X ns and if reading the data becomes available. If writing data you place on the data lines gets written. You then release CAS. On the next cycle you have the option of driving a new CAS address while the dram maintains the original RAS address. In this case you leave RAS low. This is called a page mode access. A similar access called 'static column mode' access allows you to clock successive columns without doing anything. (I believe you can clock 4 columns in without having to supply a new address). However, if the RAS address would be different you must bring RAS high (passive) for a full cycle (i.e. 80ns for 80ns DRAM) before you can begin the next cycle. DRAM requires refresh. This does NOT slow down DRAM. The reason DRAM requires refresh is because the CAPACITOR used for each memory storage cell leaks and must periodically be re-energized. > What is static column RAM? I've been told it's the same as static > RAM, but that doesn't seem right (otherwise the 3000 would be > a good bit faster and a good bit more expensive). Is it the > equivalent of what Tannenbaum calls pseudo-static? As I mentioned above, static column mode DRAM is the same as page-mode DRAM (DRAM is either one or the other type but not both) except that it uses a different access method for 'fast' accesses when the RAS address does not need to be changed. Forget pseudo static RAM, it's a complicated mess that is supposed to give a static RAM board storage capabilities similar to DRAM boards but doesn't really (you just use DRAM). > What about VRAM? Somehow specially designed for video memory, or > just some marketer's way to make the static RAM on a video card > sound superior? VIDEO DRAM is DRAM. The difference is that VIDEO DRAM has two internal FIFO's. An entire COLUMN of memory (i.e. if you have 9 address lines the DRAM addresses 9x2=18 or 256KBits with one data line, a single column represents 9 address lines or 512 bits of information). As I was saying, an entire COLUMN (even two columns depending on the design) is latched into this FIFO and may then be serially clocked out of the DRAM *COMPLETELY INDEPENDANT OF WHAT WE WOULD TERM NORMAL DRAM ACCESSES*. Specifically, you apply a video clock to the DRAM serial clock and only have to do a single random access cycle to latch in the 'next' 512 bits (or whatever, depends on the DRAM). The FIFO's are usually double buffered ... you latch data into one FIFO while the video clock is shifting data out the other. The AMIGA uses normal DRAM for its video RAM and thus the video takes a lot of bandwidth. This isn't quite fair because when you use video DRAM you are extremely limited in the resolutions you can support. > While I'm at it, why are ROMs inherently so slow? ROMs used to be slow because CMOS used to be slow (well, I am just guessing). EPROMs these days are on the average 100ns access time, up to 200ns is standard. As of 5 years ago 300ns+ was pretty standard. ROMs generally go faster... custom ROMs will run faster than static RAMs. EEPROMS and EPROMS are limited by the way cells are made. > Why is there air? A very difficult question. One might also ask "Why is there Vodka" > How many licks does it take to get to the center of a Tootsie Pop? Three! > Where's my free 68040 upgrade for the 3000 I just ordered? Comming to stores near you the moment motorola puts the stuff into mass production, assuming they fixed the problem with the chip getting so hot it has a cardiac arrest :-) -- Actually, if you are at all interested in digital design I would seriously look at HCMOS vs TTL and normal CMOS. HCMOS is a few years old and goes basically as fast as TTL (ALS, and AS in the TTL arena can really be said to go faster by any significant amount). HCMOS is great because: * CMOS power dissipation, which is 3 orders of magnitude less than TTL and an order of magnitude less than NMOS. At high frequencies HCMOS runs about an order of magnitude less power than TTL. HCMOS draw 0 power (well, a couple of picoamps actually) when idle. HCMOS power dissipation is directly proportional to the frequency at which you run it. * Symetrical output drive capability. An HCMOS output is essentially connected to BAR (+5) or GND, and the drive curves are symetrical. * CMOS DRIVE capability. Since CMOS inputs do not draw any current, a CMOS output can drive esssentially an infinite number of CMOS inputs. The limitation is in bus and input capacitance... the more capacitance you have to drive the slower the rise and fall times. HCMOS can directly drive TTL with a fanout of 10 or 20 (though TTL has problems driving HCMOS sometimes because it gets nowhere near BAR or GND in its outputs) * HCMOS has CMOS noise immunity, which means glitches on inputs can go nearly 50% of the power supply down from BAR or up from GND without effecting the output. Basically, we (where I work) use nothing but HCMOS these days. The only thing you have to be careful about is to put a small bypass capacitor across power and ground near each [H]CMOS chip... more than one would normally put on a board populated with TTL. This is because HCMOS outputs temporarily short BAR to GND when changing state (< 1ns) and while this generally does not effect other HCMOS chips due to their noise immunity, it does effect other types of chips and allowing glitches to propagate on your power bus leads to very noisy designs. > Thanks for any info you can provide. I aims to please! >-- > Gibberish Soon to be Amiga 3000 owner/fanatic! (I hope) > is spoken Contact don@brahms.udel.edu for more information. > here. DISCLAIMER: It's all YOUR fault. -- -Matt Matthew Dillon dillon@Overload.Berkeley.CA.US 891 Regal Rd. uunet.uu.net!overload!dillon Berkeley, Ca. 94708 USA
dillon@overload.Berkeley.CA.US (Matthew Dillon) (11/09/90)
In article <1990Nov08.222823.1925@hoss.unl.edu> 252u3130@fergvax.unl.edu (Phil Dietz) writes: > >I'm not too sure that TRUE statis rams are faster. In my book Computer >Organization (Hamacher Vranesic Zaky ver 3 pg 322) it quotes > >"MOS transistors are higher-impedence devices; they yield circuits that >have lower power dissipation. Their disadvantage is their slower speed >of operation." > This is true. But you can also run CMOS and HCMOS at higher voltages. The higher the voltage, the faster it goes. Normal CMOS can be run from 3V to 15V. Even at 15V normal CMOS is quite slow though. HCMOS, however, runs at the same order of magnitude as TTL with a much greater supply voltage range. You can run HCMOS from 2 to 6V. Power dissipation is directly proportional to the frequency at which you run the device AND ALSO THE VOLTAGE. This means you can *run* HCMOS at 2V and low frequency and get less than a micro-watt power dissipation *in active mode*. At 2V an idle HCMOS device pulls only leakage current which is on the order of picoamps (all the spec sheets say the leakage is in microamps but if you measure it, it's actually much, much, much less than a microamps). You can run HCMOS at up to 6V. At 6V HCMOS is *faster* than normal TTL. In comparison, TTL MUST be run between 4.5V and 5.5V, NO EXCEPTIONS. There is NO low power mode for TTL, it draws lots of current at any frequency, even at DC (no inputs changing). AS and ALS TTL is faster than HCMOS but, like TTL, also pull 3 orders of magnitude more power... that's from 100x to 1000x more power, even when running at high frequencies. Even ALS pulls a lot of power compared to CMOS/HCMOS. You also have to take fan-in and fan-out into consideration. HCMOS has much greater DRIVE capabilities (both to BAR and to GND) than TTL. >Phil Dietz -Matt -- Matthew Dillon dillon@Overload.Berkeley.CA.US 891 Regal Rd. uunet.uu.net!overload!dillon Berkeley, Ca. 94708 USA
daveh@cbmvax.commodore.com (Dave Haynie) (11/10/90)
In article <15571@brahms.udel.edu> don@brahms.udel.edu (Donald R Lloyd) writes: > Why is DRAM slower than SRAM? I can't see how having to > refresh it would cause any tremendous slowdown. The refresh, while certainly a small slowdown, it's the main reason for the difference. Perhaps the most important reason DRAM is slower than SRAM is the fact that, historically, DRAM has a muliplexed address bus. This has a tremendous savings factor in pin count -- each time you add an address line, you can quadruple the size of your memory. To access an SRAM, you provide an address to it, and one access time later, the data is valid at the output pins. Simple, straight forward. To access a DRAM, you first drive the Row address. Next, clock that into the DRAM by dropping the RAS* line (Row Address Strobe). Next, switch in the Column address, and then drop the CAS* line (Column Address Strobe). Now, based on the worst of the column access time or the remaining row access time, data will be valid on the output pins. > What is static column RAM? I've been told it's the same as > static RAM, but that doesn't seem right (otherwise the 3000 > would be a good bit faster and a good bit more expensive). > Is it the equivalent of what Tannenbaum calls pseudo-static? No, the pseudo-static RAM is kind of a weird puppy. Static column RAM is DRAM that play a trick to go a bit faster. You start out with a Row address and RAS* strobe, just like before. Then give it a Column address, but instead of a CAS* strobe, you basically have a CS* line, which acts more like a chip select and buffer enable then a strobe. Once CS* is low, you can vary your column address, and you'll get data out corresponding to that column, with the previously latched row, one column access time later. Essentially, once you've locked in the row address, the part acts like a static RAM in for the column address. And it's fast, too; typical SCRAM parts may have a row access time of 80ns-100ns, but a column access time of 35ns-50ns. The A3000 uses this feature to run the 68030 burst cycles, where the first access (in which the row address is clocked in) takes 5 clocks, but the three additional burst cycles only take two clocks each. > What about VRAM? Somehow specially designed for video memory, > or just some marketer's way to make the static RAM on a video > card sound superior? VRAM is a DRAM specially modified in a way that's useful to video displays. It has a sequential port as well as the normal random access port. Using a special cycle, you can dump an entire row's worth of data into a large shift register in one cycle. The part can then continue normal cycles, while this data is shifted out very quickly. Since video displays typically access lots of data in sequence, rather than requiring random access, this is perfect to support such displays. > While I'm at it, why are ROMs inherently so slow? You can get fast ROMs, but, like static RAM, you generally have your choice between BIG and FAST. If you're reading a normal program, like perhaps the Amiga's ROM Kernel, out of ROM, ROM density and cost are more important than speed. If the ROM costs too much, you might as well eliminate it completely and run out of RAM. In general, Speed == Money. There are very small and fast ROMs available, though they're generally used for control functions (more like a PAL), rather than main program store. Same deal with SRAM; the larger ones may be used for main program space, but they're not so fast, the smaller, faster parts are typically used for cache or similar kinds of things. > Why is there air? Why not? Seems like a good idea to me. > How many licks does it take to get to the center of a Tootsie > Pop? Three. -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Standing on the shoulders of giants leaves me cold -REM
daveh@cbmvax.commodore.com (Dave Haynie) (11/10/90)
In article <1990Nov9.005423.13745@jarvis.csri.toronto.edu> leblanc@eecg.toronto.edu (Marcel LeBlanc) writes: >252u3130@fergvax.unl.edu (Phil Dietz) writes: >>Well, everything takes time. It may only take nanoseconds to refresh >>the RAM, but it is ALWAYS refreshing the RAM. The time slowly but >>surely adds..... >But in a good design, refresh amounts to very little time. Yup. Modern DRAM, regardless of density or speed, needs one refresh cycle about every 15.6 microseconds. This amounts to roughly a 1% speed penalty if every refresh cycle contends with a desired memory cycle. In reality, though, the conflict is far less than that. On the Amiga's chip bus, DRAM refresh is just another couple chip type DMA slots, in there like floppy and sound fetch are; there's no slowdown or contention, ever. On most Zorro II memory cards, there's enough time with even 150ns to run a refresh cycle and a memory cycle for every 68000 bus cycle. On more modern designs like the 3000, the CPU is significantly faster than the memory, so refresh can only happen when necessary. In the even of a tie between a refresh request and a processor memory request, the processor goes first, then the refresh immediately after. Some memory controllers get real sophisticated and try to sneak in refreshes, or count incidental refreshes. For instance, any time you read a memory location, the whole row for that location is automagically refreshed. So if you have all memory getting the RAS* signal, and keep track of those rows addressed during a refresh period, only those not addressed need to be considered. This could be done even in the A3000, but it has some disadvantages as well, such as being memory architecture sensitive. The A3000's memory refresh logic will work with any current and very likely any future DRAM, regardless of size. >The only way ROM is going to be less expensive than RAM is if you have huge >volumes! I know I won't get a direct answer from Commodore, but can the >volume numbers for the A3000 possibly justify this? Like I said, I still >don't believe this. You really don't need such huge volumes. Let's see, 512K of DRAM is four 256K x 4 DRAMs. Even at current prices, I think ROM is still 1/2 to 1/4 the price. Even EPROM, which has been dropping in price, is getting competitive (in fact, the EPROM people have tried to convince us there's no need for maked ROMs anymore, but even a dollar or two in price difference can make a difference over the long run). >Marcel A. LeBlanc -- Electrical Eng. Computer Group, Univ. of Toronto -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Standing on the shoulders of giants leaves me cold -REM
daveh@cbmvax.commodore.com (Dave Haynie) (11/10/90)
In article <1990Nov9.075535.14012@ncsuvx.ncsu.edu> kdarling@hobbes.ncsu.edu (Kevin Darling) writes: >The A3K can use either paged or column. But while Static Column can be a >tiny bit faster, my home timing analysis indicated that it wouldn't make >any diff which one you used on the 3000. The main advantage of using static column over page mode RAM is that, with static column, you don't need to drive CAS*. So everything can be address driven, and there's no need for any additional CAS* state logic. I didn't do the Ramsey design myself, but Greg's claim is that there isn't quite enough time to build this special CAS*, at least based on the grain of the clocks used in Ramsey. But with SCRAM, it's no problem, you simply change addresses and keep CS* low. So, for an A3000 with SCRAM in it, we allow the 68030 burst cycles to be run, but they won't work with fast page mode. > Kevin Darling - "This is your | CIS: 76703,4227 Delphi:OS9ugpres -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Standing on the shoulders of giants leaves me cold -REM
johnhlee@flute.cs.cornell.edu (John H. Lee) (11/10/90)
In article <15571@brahms.udel.edu> don@brahms.udel.edu (Donald R Lloyd) writes: > Questions: > Why is DRAM slower than SRAM? I can't see how having to > refresh it would cause any tremendous slowdown. Two things: DRAM design and refresh. RAMs are arranged in a matrix with memory cells set in rows, each row sharing the same sense line. The capacitance of the sense line is non-significant. In a SRAM, each memory cell actively drives its sense line, so access is fast, but the cell is large as it requires at least 4 transistors (to form a flip-flop.) In a DRAM, each memory cell is a capacitor and a gate transistor with only the stored charged in the miniscule capacitor driving the sense line, so access is slower, but each cell can be made much smaller. Since no capacitor is perfect, periodic refresh cycles are needed to recharge the capacitors and the refresh cycles times are comparable to a normal access. A DRAM also requires a "recovery period" call pre-charge that ensures that the amps on the sense lines can detect the miniscule capacitor charges. This period is on the order of an access and is the reason why a DRAM can be accessed only half as fast as its access time. > What is static column RAM? Static column RAMs support a faster access method. A normal access requires that the address be clocked into two phases: row address with RAS (Row Address Strobe) then column address with CAS (Column Address Strobe.) Each strobe has a minimum hold time. Now a static column RAM permits both strobes to be held active and the column address to change. The RAM can provide valid data much faster since the row address is already latched and row is already accessed. > I've been told it's the same as static > RAM, but that doesn't seem right (otherwise the 3000 would be > a good bit faster and a good bit more expensive). Is it the > equivalent of what Tannenbaum calls pseudo-static? No. I believe psuedo-static RAMs only implement hidden refresh within the chip. The two concepts are not the same. > What about VRAM? Somehow specially designed for video memory, > or just some marketer's way to make the static RAM on a video > card sound superior? VRAMs are usually high speed RAMs with special features to make the video system simpler, like built-in shift registers and dual access-ports. > While I'm at it, why are ROMs inherently so slow? ROMs aren't inherently slow. However, depending on their design, ROMs may have a largely passive structure being essentially a huge, dense matrix of wires with cross-links and the capacitance of the lines affect speed. In trade journals I regularly see advertised ROMs that are as fast as high-speed RAMs. > Why is there air? Because we need something to blow the smog out of L.A. (not that it works all the time, but engineering considerations and funding impose limitations.) > How many licks does it take to get to the center of a Tootsie > Pop? Three. > Where's my free 68040 upgrade for the 3000 I just ordered? I don't know. I already got mine. :-) > Thanks for any info you can provide. You're welcome. ------------------------------------------------------------------------------- The DiskDoctor threatens the crew! Next time on AmigaDos: The Next Generation. John Lee Internet: johnhlee@cs.cornell.edu The above opinions of those of the user, and not of this machine.
stephane@Chucla.CAM.ORG (Stephane Laroche) (11/15/90)
Not so long ago I remember reading about a new kind of RAM, called FRAM. It looked like a new technology but then again, I don't know much about memories... The authors of the paper (Sorry, I can't remember who they were) basically stated that their FRAMs were similar to a EEPROM, but with reads and writes at DRAM speed. This memory, if available, would make a great replacement for ROM/EPROM chips or true recoverable ram disks. Any comments? -Stephane Stephane Laroche | Email: stephane@Chucla.CAM.ORG +1 514 277-8605 | Montreal, Que., Canada
andrew@teslab.lab.OZ (Andrew Phillips) (11/20/90)
In article <183539cc.ARN0ccd@Chucla.CAM.ORG> stephane@Chucla.CAM.ORG writes: > Not so long ago I remember reading about a new kind of RAM, called >FRAM. It looked like a new technology but then again, I don't know >much about memories... The authors of the paper (Sorry, I can't remember >who they were) basically stated that their FRAMs were similar to a EEPROM, >but with reads and writes at DRAM speed. Yes, FRAM is non-volatile RAM. I believe the technology is not very mature with only very small capacity chips currently shipping (16Kb?). Also FRAM is much more radiation hardened which has caused a lot of military interest. > This memory, if available, would make a great replacement for ROM/EPROM >chips or true recoverable ram disks. There will always be a (small?) need for non-writeable memory and ROM will probably always be cheaper to produce. But FRAM will eventually do away with the need for hard disks. -- Andrew Phillips (andrew@teslab.lab.oz.au) Phone +61 (Aust) 2 (Sydney) 289 8712
dillon@overload.Berkeley.CA.US (Matthew Dillon) (11/27/90)
It is *incredibly* easy to build a small backup circuit for static RAM.
You simply use a 0.27F (that's FARAD) capacitor for the 'backup'
supply. The RAM power bus is connected to the main board +5V (BAR) via
two transistors and a couple of resistors (voltage drop is only about
0.01V between main BAR and RAM BAR). Or, to skimp on parts you can
drop incomming power through a diode to the main bus and incomming
power through a diode to the static RAM (this prevents the backup power
from trying to drive the rest of the board). Using diodes uses more
power though since you loose 0.7V.
A single 0.27F capacitor (footprint is a little larger than a dime)
will backup 8 32Kx8 static RAMs for a heck of a long time -- several
days easy. A static RAM can generally go down to 1.5V when inactive
before it starts to loose its mind.
You must do a couple of things (even with FRAMs, most of these apply):
(1) you probably want to ensure that all tri-stated pins are pulled up
or down (usually w/ 100K resistors) to reduce wear on the drivers.
(2) Any inputs must brought low or high (usually low) via a 100K
resistor to prevent oscillations (CMOS/HCMOS parts).
(3) the RAMs must not be chip-selected during a power down. If they
are, you will generally wipe the entire RAM to garbage instead of just
a single location.
(4) Any ICs that run off the backup supply my never output a '1' state
to ICs that do NOT run off the backup supply when main power is off.
This is because static protection diodes will turn that '1' into a
short since they are connected to BAR and GND.
And, as has been mentioned, there must always be some kind of ROM or
EPROM, even if it is only an extremely small amount, to handle a cold
boot situation.
A CMOS or HCMOS part will generally pull picoamps when in standby (no
inputs changing), certainly not more than a microamp. Most static RAMs
are CMOS.
In article <1156@teslab.lab.OZ> andrew@teslab.lab.OZ (Andrew Phillips) writes:
>In article <183539cc.ARN0ccd@Chucla.CAM.ORG> stephane@Chucla.CAM.ORG writes:
>> Not so long ago I remember reading about a new kind of RAM, called
>>FRAM. It looked like a new technology but then again, I don't know
>>much about memories... The authors of the paper (Sorry, I can't remember
>>who they were) basically stated that their FRAMs were similar to a EEPROM,
>>but with reads and writes at DRAM speed.
>
>Yes, FRAM is non-volatile RAM. I believe the technology is not very
>mature with only very small capacity chips currently shipping
>(16Kb?). Also FRAM is much more radiation hardened which has caused
>a lot of military interest.
>
>> This memory, if available, would make a great replacement for ROM/EPROM
>>chips or true recoverable ram disks.
>
>There will always be a (small?) need for non-writeable memory and ROM
>will probably always be cheaper to produce. But FRAM will eventually
>do away with the need for hard disks.
>--
>Andrew Phillips (andrew@teslab.lab.oz.au) Phone +61 (Aust) 2 (Sydney) 289 8712
-Matt
--
Matthew Dillon dillon@Overload.Berkeley.CA.US
891 Regal Rd. uunet.uu.net!overload!dillon
Berkeley, Ca. 94708
USAFVEST@DUCVAX.AUBURN.EDU (Floyd Vest) (11/29/90)
Andrew Phillips <andrew@teslab.lab.oz> wrote: >In article <183539cc.ARN0ccd@Chucla.CAM.ORG> stephane@Chucla.CAM.ORG writes: >> Not so long ago I remember reading about a new kind of RAM, called >>FRAM. It looked like a new technology but then again, I don't know >>much about memories... The authors of the paper (Sorry, I can't remember >>who they were) basically stated that their FRAMs were similar to a EEPROM, >>but with reads and writes at DRAM speed. >Yes, FRAM is non-volatile RAM. I believe the technology is not very >mature with only very small capacity chips currently shipping >(16Kb?). Also FRAM is much more radiation hardened which has caused >a lot of military interest. >> This memory, if available, would make a great replacement for ROM/EPROM >>chips or true recoverable ram disks. >There will always be a (small?) need for non-writeable memory and ROM >will probably always be cheaper to produce. But FRAM will eventually >do away with the need for hard disks. Given past development cycles, you are looking at 1995-96 before dense enough chips are produced to seriously challenge today's HD. However, that may not be enough...by that time you will be competing with magneto-optical drives with Terrabyte capacities. DRAM technology should be providing chips in the 32-64Mb range. One market that will avail itself...hand-held instruments--computers, games, elctronic books, and telephone. Another application would be the ease with which operating system upgrades could be made [Call 1-900-AMIGA3.0--$49.95 (19.2/38.4/154 KB)]. Any idea who is developing FRAM? Could be an investment here :-) -- Floyd Vest Auburn University ##### fvest@ducvax.auburn.edu ##### +1 205 844 4512 Auburn, Alabama USA FIDO: 1:3613/3