apm279l@vaxc.cc.monash.edu.au (11/28/90)
Hey, sorry guys but I posted 1/2 an hour too soon! Just got the following from Alonzo who asked me to post it: >From: IN%"microsoft!alonzo@murtoa.cs.mu.oz@uunet.uu.net" 28-NOV-1990 11:04:18.59 >To: APM279L@vaxc.cc.monash.edu.au >CC: >Subj: Carry clarification > >Received: from munnari.OZ.AU by vaxc.cc.monash.edu.au; Wed, 28 Nov 90 11:03 > +1100 >Received: from murtoa.cs.mu.OZ.AU by munnari.oz.au with SMTP (5.64+1.3.1+0.50) > id AA01210; Wed, 28 Nov 1990 11:02:56 +1100 (from > microsoft!alonzo@murtoa.cs.mu.oz@uunet.uu.net) >Received: from uunet by murtoa.cs.mu.OZ.AU with UUCP (5.61+IDA+MU) id AA09918; > Wed, 28 Nov 1990 11:02:41 +1100 (from uunet!microsoft!alonzo for > APM279L@vaxc.cc.monash.edu.au) >Received: from microsoft.UUCP by uunet.uu.net (5.61/1.14) with UUCP id AA09694; > Tue, 27 Nov 90 18:51:58 -0500 >Date: Tue, 27 Nov 90 18:51:58 -0500 >From: microsoft!alonzo@murtoa.cs.mu.oz@uunet.uu.net >Subject: Carry clarification >To: APM279L@vaxc.cc.monash.edu.au >Message-id: <9011272351.AA09694@uunet.uu.net> >X-Envelope-to: APM279L > >Here are the answers to your questions, with some help from a higher >authority (HA). Please repost to comp.sys.handhelds and save me the effort. > >Alonzo > >| (1) According to the now biblical processor notes (thanks Alonzo!) >| the branch instructions affect the carry. I need to know *how* >| it is affected. I *guess* that (for example) brgt.f a,c,label >| does a subtraction, but is it "a-c" or "c-a"?? what about >| breq, brge, brle, brlt etc. What about brz and brnz?? > >If the branch is taken (i.e., the test is true) the carry bit is set. > >| (2) What about neg.f X - how is carry altered? It could either take >| a two's complement by inverting and THEN incrementing, or by >| decrementing, THEN inverting. > >Seems to me that the NEG instruction will set carry according to whether >the result is 0. This is the only case where decrementing before inversion >or incrementing after inversion will cause overflow. The order of operations >is therefore irrelevant. Try it and see. This command performs a 2's >complement, or 9's complement, depending on the DEC/BIN mokde. > >The NOT instruction performs a 1's complement, or 10's complement, depending >on the DEC/BIN mode. It clears the carry bit. > >| (3) gosub, gosubvl, gosubl also affect carry - is this because the processor >| takes PC.a+OFFSET.a ? > >I am told that this is absolutely untrue. They do not affect carry. > >| (4) How do the IN and OUT registers get used? (I know they are used somehow >| for I/O - but what happens, for example when you put something in OUT, >| how does IN receive input? and from where? - I though the keyboard was >| bufferred in memory (#F.... something) > >It's a cool idea to add stuff to the bus and do IO, but I'm not a >hardware junkie. The instructions OUT=C and OUT=CS send the X or least >significant nibble of C. The instructions A=IN copies IN into nibbles >0 through 3 of A, and C=IN does likewise to C. --HA > >| (5) What's known about the BUS commands? (BUSCB, BUSCC, BUSCD - do these put >| the contents of B,C or D on the bus? if so, what field is put?) >| CON/UNCONFIG, MOVE.A ID,C, SREQ, RESET. - I have the brief descriptions >| of these from Alonzo's notes, but what are the chips in question? What >| are the ID's, what happens when you config/unconfig/reset the chip? > >The bus commands issue a sequence that is intrepreted by the chips on >the bus - they do not send register contents. Unless you are adding >Saturn chips to the bus that are smart enough to interpret bus commands >and not torch the 48's configuration, there's no reason to support these >instructions. They were most useful on the 71, but since the 48's >address space is spoken for, they're just PLA wasters now. --HA > > >Alonzo Gariepy >alonzo@microsoft Thanks to AG and HA for that. Well I'll post my debugger today or tomorrow. Peter