MBF@cmu-cs-c.arpa@sri-unix.UUCP (05/20/83)
Anybody SERIOUSLY interested in the MOS Technology 6509 should scrap that chip and take a look at Rockwell's recent introductions. Unfortunately, they seem to be heading in two disparate directions (at least for now!). First, the CMOS: they are now sampling and shipping limited quantities of 65C02[A] (1 [2] MHz clock) chips and expect to be shipping the 4MHz chip soon. Imagine, a 4MHz 6502! Zilog, stuff your 6MHz Z80 ... well, almost. Some of the big wins of the CMOS 6502's are (from memory): real DMA capability because you can now do bus request/grant operations to tri-state the bus (this is really just a convenience feature - people worked around the lack before); power dissipation of 4mA/MHz (that's right - 80mW power dissipation from a 4MHz 6502!); and an extended instruction set that will really appeal to 6502 hackers - admittedly, it doesn't make the 6502 a competitor for the 6809 in terms of "instruction set usability", but it goes a long way toward fixing many of the glaring omissions of the standard 6502 opcodes. Examples: now we can inc/dec the accumulator; use a non-indexed indirect (like (),y without the ",y") on many instructions (truly useful!); a jmp indirect-indexed which makes non-relocatable jump tables a breeze by replacing a slew of bytes; some new instructions: stz (STore Zero), bra (BRAnch uncdx), phx/plx/phy/ply (push, pop x or y); and a gaggle of bit-manipulation instructions. Other features include typically wide CMOS power supply range (3-6V); "Memory Lock" output which tells you to prevent other CPU's from getting the bus now because the "locked" CPU is executing a read/modify/write instruction; and a single-quantity cost of under $12!! The chip comes in three versions (now), one of which is plug-compatible with the MOS Technology/Rockwell/ Synertek CPU's in your Apples, Ataris, VICs, etc... On the other hand, their NMOS line is not dying out, either: the main extension is a family of chips with additional hardware on-chip. The 6511[A]Q is the flagship of the new family, intended for prototyping. The other three chips have varying amounts of on-chip ROM for production-level circuits. The disparity between these chips and the CMOS family is unfortunate; for instance, the 6511 line also has an extended 6502 instruction set, which sadly adds only 4 new bit-manipulation instructions. Also, power consumption is hardly stingy. Nevertheless, on with the good news! The chip has 192 bytes of RAM, 32 of which are battery-backuppable (!), 4 8-bit TTL-compatible I/O ports (a little tricky, the chip comes on a 64-pin QUIP!), two 16-bit counter/timers (like a VIA), a programmable-bit-rate UART with a neat wake-up feature for networking slaves in a system (can also do synchronous I/O w/ baud rate up to 62.5Kbps), 10 vectored (!) interrupts (2 for counters, 4 edge-sensitive I/O lines, NMI*, RES*, and Serial Data Xmit/Rcvd), and 1- or 2-MHz clock. Contrast this chip with a MosTechnology 6509!! Note also that these parts are available now! Happy designing, Mark Dzmura via mbf@cmu-cs-c quick p.s.: the ROM versions of the 6511Q are the 6500/11, /12, and /13. I don't remember which is which, but the neatest comes with 3K bytes of ROM on-chip! -------