garyf@jpl-devvax.jpl.nasa.gov (Gary Friedman) (03/14/91)
In article <5397@male.EBay.Sun.COM> wag@georwell.EBay.Sun.COM (Rick Wagoner) writes: > >Does anyone have a pinout for the Plug in cards for the >'48 (IE the Equation card, 41 Emulator)? I just happen to have a copy here. The document is titled "HP48SX Expansion Port - Technical Guide and Specification", dated November 12, 1990. When looking at the card contacts, pin one is on the right: PIN # Signal I/O Description ----------------------------------------------------------------- 1 VDD PI Power 2 VBB O Card battery check. If VBB is low then 48SX will signal 'low battery'. 3 A0 I Pins 3-19, 31, and 32 are the address lines. (Pin 32 is inverted.) My guess is the 20th address line is actually the Card Enable (pin 21) input in disguise. 4 A1 I 5 A2 I 6 A3 I 7 A4 I 8 A5 I 9 A6 I 10 A7 I 11 A8 I 12 A9 I 13 A10 I 14 A11 I 15 A12 I 16 A13 I 17 A14 I 18 A15 I 19 A16 I 20 NWE I Not write enable 21 CE I Card Enable 22 NOE I Not output enable 23 D0 I/O Pins 23-30 are the eight data lines. 24 D1 I/O 25 D2 I/O 26 D3 I/O 27 D4 I/O 28 D5 I/O 29 D6 I/O 30 D7 I/O 31 A17 I 32 NA18 I A18 is inverted (negative logic) 33 XSCL I Display data clock 34 LP I Display data horizontal sync 35 LD[0] I Display data 36 LD[1] I Display data 37 CDT O Card detect/type, must be tied high for writes to operate. 38 NC No connection. 39 NC 40 GND PI Ground The CDT pin (37) helps the 48 determine which of the following four valid states applies: 1) Empty - The CDT pin is open (Hi Z). 2) ROM - The CDT pin is low. All write operations are disabled. 3) RAM - The CDT pin is high and the card passes the RAM size test. 4) UNKNOWN DEVICE - The CDT pin is high and the card fails the RAM size test. User-level reads and writes are disabled (as if nothing were present) but machine level reads and writes work. Lines 33-36 are responsible for those overhead projector thingys (that's the technical term) which frame grab the 48's display and uses the bitmap for its own purposes. The data is two serial bit streams in sync with the shift clock XSCL. A pulse on the LP signal provides horizontal sync information. The 131 columns of display data for a particular row are contained in the 64 shifts before each LP pulse and the 2 shifts immediately following the LP. The left-most column of data is output first. There is no vertical sync. *Whew!* -Gary Friedman ---------------------------------------------------------------- Gary Friedman Jet Propulsion Laboratory - NASA 4800 Oak Grove Drive, Pasadena, CA. 91109 (818) 354-1447 garyf@puente.JPL.NASA.GOV || {cit-vax,elroy,psivax}!devvax!garyf Newsgroups: comp.sys.handhelds Subject: Re: HP48SX Plug in Card Pin outs and a question References: <5397@male.EBay.Sun.COM> Organization: Jet Propulsion Laboratory, Advanced Engineering Group In article <5397@male.EBay.Sun.COM> wag@georwell.EBay.Sun.COM (Rick Wagoner) writes: > >Does anyone have a pinout for the Plug in cards for the >'48 (IE the Equation card, 41 Emulator)? I just happen to have a copy here. The document is titled "HP48SX Expansion Port - Technical Guide and Specification", dated November 12, 1990. When looking at the card contacts, pin one is on the right: PIN # Signal I/O Description ----------------------------------------------------------------- 1 VDD PI Power 2 VBB O Card battery check. If VBB is low then 48SX will signal 'low battery'. 3 A0 I Pins 3-19, 31, and 32 are the address lines. (Pin 32 is inverted.) My guess is the 20th address line is actually the Card Enable (pin 21) input in disguise. 4 A1 I 5 A2 I 6 A3 I 7 A4 I 8 A5 I 9 A6 I 10 A7 I 11 A8 I 12 A9 I 13 A10 I 14 A11 I 15 A12 I 16 A13 I 17 A14 I 18 A15 I 19 A16 I 20 NWE I Not write enable 21 CE I Card Enable 22 NOE I Not output enable 23 D0 I/O Pins 23-30 are the eight data lines. 24 D1 I/O 25 D2 I/O 26 D3 I/O 27 D4 I/O 28 D5 I/O 29 D6 I/O 30 D7 I/O 31 A17 I 32 NA18 I A18 is inverted (negative logic) 33 XSCL I Display data clock 34 LP I Display data horizontal sync 35 LD[0] I Display data 36 LD[1] I Display data 37 CDT O Card detect/type, must be tied high for writes to operate. 38 NC No connection. 39 NC 40 GND PI Ground The CDT pin (37) helps the 48 determine which of the following four valid states applies: 1) Empty - The CDT pin is open (Hi Z). 2) ROM - The CDT pin is low. All write operations are disabled. 3) RAM - The CDT pin is high and the card passes the RAM size test. 4) UNKNOWN DEVICE - The CDT pin is high and the card fails the RAM size test. User-level reads and writes are disabled (as if nothing were present) but machine level reads and writes work. Lines 33-36 are responsible for those overhead projector thingys (that's the technical term) which frame grab the 48's display and uses the bitmap for its own purposes. The data is two serial bit streams in sync with the shift clock XSCL. A pulse on the LP signal provides horizontal sync information. The 131 columns of display data for a particular row are contained in the 64 shifts before each LP pulse and the 2 shifts immediately following the LP. The left-most column of data is output first. There is no vertical sync. *Whew!* -Gary Friedman ---------------------------------------------------------------- Gary Friedman Jet Propulsion Laboratory - NASA 4800 Oak Grove Drive, Pasadena, CA. 91109 (818) 354-1447 garyf@puente.JPL.NASA.GOV || {cit-vax,elroy,psivax}!devvax!garyf -- ---------------------------------------------------------------- Gary Friedman Jet Propulsion Laboratory - NASA 4800 Oak Grove Drive, Pasadena, CA. 91109 (818) 354-1447 garyf@puente.JPL.NASA.GOV || {cit-vax,elroy,psivax}!devvax!garyf