grue@cs.uq.oz.au (Frobozz) (04/11/91)
hiya,
I'm writing a small (??) program for the 48 and I would like to know
some details about the timing of some of the instructions available (I don't
have the tech doc for the Saturn processor). I particular, I would like to
know the timings of the following (using Alonzo's notation):
81A?0? Move.? a/c, r?
81A?1? Move.? r?, a/c
81A?2? Swap.? a/c, r?
10? Move.w a/c, r?
11? Move.w r?, a/c
12? Swap.w a/c, r?
BF? Srn.w reg ? = [4,5,6,7]
81? Rrn.w reg ? = [4,5,6,7]
These are the move from either a or c into one of the temporary registers for
the various different fields. (I really like the way that you can specify the
.w field in 2 different instructions).
Also the following would also be helpful:
13? swap.a a/c, d?
14? move.a ?, ? indirect memory references
16? add.a ?+1, d0
18? sub.a ?+1, d0
These are the shift/rotate right by nibble instructions.
My problem is that I am going to require more data space that there are
registers in the processor. Due to the limited ranges of the data that
is going to be kept around, I would be able to stuff more than one item
into each CPU register (who really needs 64 bits anyway). I was wondering
what the performance hit would be like to use the shift/rotate instructions
to grab bits out of the registers as well as the cost of transfering stuff
from the temp registers to the cpu registers. The alternative to over using
the CPU registers is to define an area of memory and indirectly address that
(I won't be able to dedicate an address register to this task but I would be
able to cache the address in one of the temp registers).
Pauli
seeya
Paul Dale | Internet/CSnet: grue@cs.uq.oz.au
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--akcs.scotty@hpcvbbs.UUCP (SCOTTY THOMPSON) (04/13/91)
I, too, would like timing information on the Saturn CPU Registers. M/L Hacker I am, I'm surprised no list has them. Scott Thompson 1621 W. 257th St. #2 Harbor City, CA 90710 (213) 539-3611 (Wk), (213) 539-9780 (Hm) Thanks...
akcs.joehorn@hpcvbbs.UUCP (Joseph K. Horn) (04/23/91)
Paul Dale (aka grue@cs.uq.oz.au, Frobozz, and Pauli) on Thu Apr 11 1991 wrote: > I'm writing a small (??) program for the 48 and I would like to know > some details about the timing of some of the instructions available > (I don't have the tech doc for the Saturn processor). I particular, > I would like to know the timings of the following (using Alonzo's > notation): > > 81A?0? Move.? a/c, r? > 81A?1? Move.? r?, a/c > 81A?2? Swap.? a/c, r? > 10? Move.w a/c, r? > 11? Move.w r?, a/c > 12? Swap.w a/c, r? > BF? Srn.w reg ? = [4,5,6,7] > 81? Rrn.w reg ? = [4,5,6,7] > [...] > 13? swap.a a/c, d? > 14? move.a ?, ? indirect memory references > 16? add.a ?+1, d0 > 18? sub.a ?+1, d0 Hope this isn't too late, Paul: The 81A??? opcodes are "new" (not found in the HP 71) and therefore not documented in the 71 IDS, which is the only Saturn timing info we have. 10?, 11?, 12? and BF? take 19 clock cycles. Rrn.w reg takes 21 cycles. 13? Swap.a a/c,d? takes 8 cycles. 14? Move.a ?,? (indirect) takes 17 cycles. 16? Add.a ?,d? takes 7 cycles. 18? Sub.a ?,d? takes 7 cycles. The accuracy of the above is not guaranteed, since the microcode for these instructions may have changed since the HP 71. The loose rule of thumb I use is that an instruction takes as many clock cycles as the number of digits in its opcode PLUS the number of digits of data that are operated upon. -- Joseph K. Horn -- Peripheral Vision, Ltd. --