Jake-S@cup.portal.com (Jake G Schwartz) (06/17/91)
With regard to the HP48 dropping keypresses especially during turnon, I think the fact that the Corvallis people admitting that the '48 was pushing the 2 MHz Saturn just about as far as it could be pushed says it all. In the talk that Bill Wickes gave on Saturday evening, June 2, 1990 (following the formal Chicago Area HP Conference last year) he mentioned that the team had wished that they could have added some real estate on that latest implementation of the Saturn chip, in order to have some additional registers. This, he said might have sped up quite a few aspects of the RPL system. I personally am not unhappy with the system the way it is functionally, but we all could use more speed. Bill also mentioned in Philly back last November that the guys had experimented with an implementation of a subset of the RPL system on an 8088 machine, and that they had achieved a 2-to-1 speedup. (He said that he personally was not satisfied with that; that 5 or 10 to 1 would have been more desirable.) With all the emphasis in the software world that I work in on code reuse, I can see a great benefit to HP Corvallis if they were to consider redoing the Saturn chip for the next go around, rather than attempting to port everything over to somebody else's hardware. With RPL as we know it running on a chip with all the hardware on their wish-list, plus a significantly faster clock (say, 10 MHz?), perhaps the speed and power issues of the HP48 would become moot.
bson@rice-chex.ai.mit.edu (Jan Brittenson) (06/17/91)
In a posting of [16 Jun 91 17:05:12 GMT] Jake-S@cup.portal.com (Jake G Schwartz) writes: > Bill also mentioned in Philly back last November that the guys had > experimented with an implementation of a subset of the RPL system on > an 8088 machine, and that they had achieved a 2-to-1 speedup. Maybe, but the Saturn CPU today is only a cell in a custom chip, no? Since given the instruction timings it seems to be a 4-bit CPU (although with a 64-bit architecture), it is probably a fairly small cell as well. I'm sure that if there were space for it, a huge speed gain could be made by widening the external data bus and making all internal data paths (and the ALU) 20 bits (5 digits). For numerical crunching, the 64-bit architecture certainly is just great. Perhaps microcoded (up to full 64-bit) multiplication and division could improve trig and log speeds. -- Jan Brittenson bson@ai.mit.edu