jwmills@iuvax.cs.indiana.edu (Jonathan Mills) (03/02/90)
In article <9003020522.AA25938@megalon.acad.com> Rudy Rucker writes: > >Using a lot of states to represent all components is a nice idea. You >can have states 0 thru 255, so you can have a cell that is aan and gate, >a cell that is an or gate, a cell that is a source of faults, etc. >So then you can make tiny tiny wireworld circuits. And animate them. >Chip designers use something like this, I guess, tho they run slowly? I've investigated cellular automata for VLSI simulation and verification, and am still working with it. But no tools, either mine or others I am aware of (various signal-level circuit simulators, digital simulators, or symbolic simulators) use the wireworld approach of "duelling electrons." It's cute, but it is too far divorced from the properties of the circuits to be useful (IMHO; no insults to clever originators of concept or the wireworld program; flames to /dev/null). Circuit simulators commonly used solve for increasingly complex sets of partial differental equations (from what I've seen of Spice documentation), and attempt to find the fixpoint of that set of equations (i.e., "converge"). Sometimes they don't. The VLSI CAs I've worked with model various transistors, gates, oscillators, and networks, and can be compiled from MAGIC layouts -- although I haven't automated the process. Their behavior is similar -- but not identical -- to the "real" thing, in part because the model embedded is _much_ less complex. Certainly the VLSI CAs _do_ run slowly; they are not realistic for circuits of interest. Consider that university tools (Spice, again) may run for days to compute the behavior of a complex circuit. Sincerely, Jonathan
karakots@apple.com (Ken Karakotsios) (03/03/90)
There are several aspects of VLSI design that one uses computers for: Logic simulation, timing accurate simulation, layout generation, design rule checking, static timing analysis, schematic extraction from a layout (for checking to make sure your layout generator did its job), and modelling the solid state physics of a single transistor are a few examples that come to mind. Wire world running on a serial computer is many orders of magnitude slower than current logic simulators. Also, the fact that synchronization of electorns at gates requires all paths between gates to be the same length makes things quite complicated. However, one company I know of (Qucikturn) is using a large cluster of electrically programmable gate arrays to actually implement the logic, on the fly, that you want to simulate. This approach sounds about as reasonable as making a special electrically programmable wireworld hardware element to do logic simulation. Put a reconfigurable cluster of enough of them together (is this a CAM-8?) and you could get one clock cycle of the design you are simulating in some small number of clock cycles of the wireworld simulator hardware. Typical logic simulation of a complex design on a serial computer is about a factor of 10^6 slower than the speed of the real design. If you can do better than this with a cheap hardware add-on, it could be interesting. Perhaps CAs could be applied the problem of generating VLSI layout or extracting a schematic from existing layout. For example, you could use a CA which shrinks rectangles down to lines to simplify the topology of a VLSI layout into some "stick" types of patterns. Perhaps these patterns could then be looked up in some "list of possible patterns". Static timing analysis requires software which can find all possible paths which a signal can take through a design. Maybe "virtual ants" could crawl through the netlist and report back to some data structure on what all the paths are... Ken Karakotsios karakots@apple.com (408) 974-1942 AppleLink: karakots generic disclaimer... I speak for myself, not Apple...