[net.micro] Some 386 rumors

kavaler@ucbcad.UUCP (07/02/83)

#N:ucbcad:5000003:000:2615
ucbcad!kavaler    Jul  1 15:00:00 1983

Here are some of the answers to my questions on the Intel 386:

1.  The people at Intel say "it is a 32 bit 286."  Whatever that means.
    The 286 has 16 bit addresses in its instructions therefore there must
    either be a new instruction set, or a speed-up of the old change
    segment instruction, or a 32-bit, 16-bit mode flag (like the real/
    virtual addressing mode).  I suspect that Intel chose the 32/16 bit
    flag since this seems to be their style.  They are commited to the
    8086 instruction set (just as IBM is commited to the 360 instruction
    set).  I suspect that the 386 will have to be upward compatible
    in the sense that it can still run all the old 8086 instructions, but
    probably will concentrate more on new features.

2.  Rumor:  The 386 will have a writeable control store, i.e. you can
    design you own instructions in microcode.  This is a big step for
    micro-computers.

3.  Rumor:  The 386 will have a 32 bit segment address as well as a 32
    bit "instruction address."   This seems like the reason for the comment
    on page 16 of the 286 spec sheets "must be set to 0 for iAPX compatability"
    although their would have to be both a 32 bit base and 
    limit register otherwise there is still a problem that segments
    can are 16 bits.

4.  Rumor:  The 386 will have paging support.  I report this because
    an Intel employee wrote to me (on the net) that he cannot comment
    on the paging support.  Actually, this doesn't mean anything, but I
    think it was his saying that "although Intel (the company) won't let
    me tell you about it, I can drop strong hints."  Take this rumor with
    a grain of salt.

5.  As for the 386 being a combination 286/186, I doubt it.  It would be
    extremely difficult to add all of the features in the 386 (i.e. 32 wide
    everything) and still have enough room left over for a timer, dma, etc.
    I could be wrong about this.  With regards to an on-chip video generator,
    this I can almost say will not happen.  The video would require
    at least 2k bytes (16k bits) of memory (on chip) as well as a look-up
    ROM (also 16k bits).  If a bit-mapped scheme is used then there
    certainly wouldn't be enough memory on-chip.

All in all I would say that Intel would probably do better to tell people
what their chip is going to have on it than to sit on their "trade secrets".
The only conclusion that I can draw from Intel's unwillingness to tell people
what is in the 386 is that it is still not any better than previous x86 chips.


Robert Kavaler   (kavaler@ucbmedea APRA, ucbcad!kavaler UUCP)