gillies@uiucdcsp.cs.uiuc.edu (03/27/88)
The privileged 68020 MOVEC command lets you move data to the CPU control register. One particular cache control register (CACR) controls the cache: Assembler: MOVEC Rc,Rn MOVEC Rn,Rc Description: Copy the contents of the specified control register (Rc) to the specified general register or copy the contents of the specified general register to the specified control register. This is always a 32-bit transfer even though the control register may be implemented with fewer bits. Unimplementeod bits are read as zeroes. Instruction Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +----------------------------------------------------------------+ | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | dr | +---+-----------+------------------------------------------------+ |A/D| Register | Control Register | +----------------------------------------------------------------+ Instructions Fields dr field -- specifies the direction of the transfer 0 control register to general register 1 general register to control register A/D field - specifies the type of general register 0 data register 1 address register Register field - specifies the register number (R0-R7) Control Register field - specifies the control register HEX -------------------------------- 000 SFC 001 DFC 002 CACHE CONTROL REGISTER (CACR) 800 USP 801 VBE 802 CAAR 803 MSP 804 ISP The bits of the CACHE CONTROL REGISTER are: 31.....t 8 7 6 5 4 3 2 1 0 ------------------------------------------------- 0...... 0 0 0 0 0 C CE F E E-Enable Cache. This bit allows the programmer to operate the processor with the cache disabled. The cache will remain disable as long as this bit is cleared. The bit is automatically cleared whenever the processor is reset, to enable the cache. F-Freeze cache. Keeps the cache enabled, but cache misses do not cause a value in the cache to be replaced. CE-Clear Entry. Used, with the CAAR register, to clear a particular entry in the cache. C-Clear Cache. The Cache clear bit invalidates all entries in the cache. A write to the cache control register with this bit set causes the cache to be cleared. The bit always reads out as zero.