chris@mddc.UUCP (08/08/83)
Just read (in MIS weekly) about the Pyrmid 90x;
"The first machine design to run Unix".
Does anyone know anything about this machine?
Chris Maloney
{...decvax!cbosgd!mddc!chris}mjl@ritcv.UUCP (Mike Lutz) (08/10/83)
There's an article on the Pyramid 90x in the August 11 issue of
Electronics, pp. 149-150. It seems to be a commercial approximation to
the RISC I from Berkeley. It's a load/store architecture, has 32
addressable registers within each function/procedure, and uses the RISC
I overlapping register windows to provide for efficient parameter
passing and function invocation. It's not a VLSI device like RISC;
instead it's TTL-based using microcoded control. Pyramid is quoting a
2-5 factor of improvement over an 11/780.
Mike Lutz
{allegra,seismo}!rochester!ritcv!mjlpollack@uicsl.UUCP (08/11/83)
#R:mddc:-20900:uicsl:7000019:000:909 uicsl!pollack Aug 10 16:50:00 1983 A salesman and the chief engineer from Pyramid Technologies came and gave us a pitch on their machine. Although it probably doesn't belong in net.micro, here are some notes I took on it: motto: "A Superior Unix-based SuperMini Computer, Tailorable over Time" runs Bell Unix V5 (with some Berkeley enhancements) Uses a common tree-based intermediate language for all its compilers, which provides lots of optimization Claim of 2-4 time Vax780 performance 32 bit data and address paths VM with 2k blocks Small Instruction set (ala RISC) Very Large Register set (528 32bit regs!) 125ns cycle time 32Mb/sec bus 40 card slots (plus optional extra box) Small physical dimensions: approximately 25"b 40"d 51"h Sample Price: 4Mb of memory, 16 users, 380Mb Disk = $125K I have the phone number of the VP in charge of sales, if you need it. Jordan Pollack Univ. of Ill. ...!pur-ee!uiucdcs!uicsl!pollack
lee@ut-ngp.UUCP (08/11/83)
The Pyramid 90x that was described in the August 11 issue of Electronics is an interesting machine. It is a reduced instruction set (RISC) system that will eventually support multiple CPUs in a very closely coupled environment (on the same bus). The present system is a single CPU that can have multiple "performance modules". An terminal controller offloads some of the tty driver work from the CPU; there is a floating point board and an array processor board; and several other possibilities. The people at Pyramid seem to be very sharp and understand Unix well. They are (will be) selling a combination Berkeley 4.2 and System 5 with the 4.2 TCP/IP networking code. It appears to be a high performance system. Pyramid claims 2 to 5 times faster than a Vax 780. I played briefly with a prototype system at NCC. Pyramid had just gotten the machine up a few weeks before so there were still some missing pieces but it was fast for doing C compiles (noticeably faster than an unloaded 780). Their prices are generally less than for Vaxes ($100K - $300K). Pyramid claims their 90x can support 128 interactive users. They have a 32 MB/sec bus and an interesting register set (528 registers). A memory cache also improves performance (Pyramid claims 80% to 85% cache hits). Memory management (using the 4.1C demand paging algorithm) supports up to 8 MB real memory with 4K instruction cache and 32K data cache (125 ns cache). With 256K chips, main memory can be expanded to 32MB real memory. Pyramid has already installed their first beta system at a major Eastern University and expect to start shipping "real" customers this fall. Pyramid is located at 1295 Charleston Rd., Mountain View, Ca. 94043. Phone number is (415) 965-7200. Bill Lee University of Texas The above information is from discussions with Pyramid and the article in Aug 11 Electronics. I am not affiliated in any way with Pyramid Tech.