jskuskin@eleazar.dartmouth.edu (Jeffrey Kuskin) (01/30/89)
A question for Mac hardware types: I am designing a hardware monitor for a Mac SE. It will be constructed on an expansion card and will record (in onboard SRAM) all CPU instruction fetches. That is, it will record the address from which the instruction was fetched as well as the instruction itself. To determine the address of the fetch I simply have to store the data on the address bus when /AS (Address Strobe) falls. (I also have to examine the FC2-0 lines to determine if the 68k is making an instruction fetch in the first place, of course.) The instruction itself will appear sometime later on the data bus. The problem: What signal can be used to latch the instruction off the data bus? My initial thought was /DTACK, but the "Designing Cards and Drivers for the Mac II and SE" book says that /DTACK is generated by the BBU well before the data bus is valid. (Specifically, the BBU generates /DTACK in bus cycle state S4 while the data bus is not valid until 15ns into state S7.) Furthermore, the book says that the data bus must remain valid only until /AS or /CAS rises, whichever occurs first. But the timing diagram in the book (Fig. 13-2) shows /AS rising in state S7, therefore seeming to imply that /AS could rise before the data bus was ever valid (and you thought the Mac didn't have DMA...) So, the question remains: What signal can be used to latch valid data off the data bus during a RAM read cycle? Will /PMCYC going high in state S0 do the trick? Thanks for any insight. Please e-mail your comments to: jskuskin@Eleazar.Dartmouth.EDU -- Jeff Kuskin, Dartmouth College