rampil@cca.ucsf.edu (Ira Rampil) (11/15/89)
Does anyone know the mapping between the four registers per channel mentioned in IM (ie Read(data,ctl), Write(date,ctl)) and the eight READ registers and 16 WRITE registers that the SCC actually has? I need to RESET CTS IE and DCD IE in WR15 and then poll RR0 (probably the IM ReadCTL) in a Time Manager Task to check the current state of these input lines. Please E-Mail or Post, as you desire! Many Thanks, Ira
aw0g+@andrew.cmu.edu (Aaron Wohl) (11/15/89)
Low memory locations containing the addresses: SCCRd - 0x1D9 SCCWr - 0x1DC Constants: #define bCtl 0 /*offset to SCC B control port*/ #define bData 4 /*offset to SCC B data interupt*/
rampil@cca.ucsf.edu (Ira Rampil) (11/16/89)
Thanks to the folks who responded to my query. Unfortunately, Reprints of the SysEqu table from IM don't help. IM gives the vector to 4 registers of the SCC. IM uses 'strange' names (not Zilog) for these registers, though it seems clear that READ CTL is (Zilog) RR8. I need access to several of the Zilog registers ( there are more than 40!). If someone in authority knows that the address mapping is linear that would be enough. Thanks! Ira "I deny nothing!" - STIV
amanda@intercon.com (Amanda Walker) (11/16/89)
In article <2573@ucsfcca.ucsf.edu>, rampil@cca.ucsf.edu (Ira Rampil) writes: > IM uses 'strange' names (not Zilog) for these > registers, though it seems clear that READ CTL is (Zilog) RR8. I need > access to several of the Zilog registers ( there are more than 40!). Take another look at your Zilog databook. The SCC uses a register- pointer scheme to minimize the number of I/O addresses it takes up on the host's address bus. For example, to write to any register beside WR0, you write the register number into the control port for the channel you want, and then the next write done to the data port for that channel will be routed to the appropriate SCC register. Reading works in a similar way. This is how the SCC was designed; it's not a result of the Macintosh I/O architecture. On the Mac, the host addresses are different for reads and writes, so you need to add the appropriate offsets for the A & Bcommand & data ports to the read or write base addresses, but aside from that, using the SCC from the Mac is quite straightforward. Amanda Walker <amanda@intercon.com> --