hsplab@ecsvax.UUCP (01/02/84)
The sMEMR pin (pin #47) is used for a memory read status signal, not
for memory refresh. Some manufacturers did use an undefined line
(pin 66 I think) for the refresh signal, but this was never officially
sanctioned in the IEEE-696 standard. This is in part a result of the
ability to derive the necessary status signals from the existing buss
status signals (e.g., through the use of the sM1 and clock signals).
Unfortunately, there is also a great deal of processor dependance and
if DMA was used, some means of accommodating that was also needed. This
is probably the main reason why some manufacturers, such as COMPUPRO
refrained from using dynamic memories on the S-100 buss. It is possible
to design good dynamic memory, but generally such designs need to know
about all possible conflicts for the refresh signals, especially the
temporary buss masters such as disk DMA.
D. Chou
University of North Carolina, Chapel Hill
...{unc,mcnc,duke}!ecsvax!hsplan
thats hsplab, not hsplan
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